International Business Machines Corporation

Brian J Machesney

Edward J Nowak

Jack Allan Mandelman

Michael A Leach

John Edward Cronin

Pai-Hung Pan

Carter W Kaanta

Nicky C Lu

Hing Wong

Michael L Kerbaugh

Charles W Koburger, Iii

Paul Christian Parries

Donald M Kenney

Howard Smith Landis

Michael D Armacost

Rosemary A Previti-Kelly

Glen L Miles

Roderick Michael West

Rick L Mohler

John F Rembetski

Chung-Yu Ting

Somanath Dash

James K Paulsen

Christopher R Whitaker

Daniel J Venditti

Stephen D Warley

Nitin B Parekh

Michael M Armacost

A semiconductor chip with uniform topology includes a memory cell having a stacked capacitor self-aligned with a bitline. Thick insulation on the bitline and on interconnect wiring on supports circuits of the chip serves to provide the uniform topology and to provide for the self-alignment of the capacitor and bitline. Bitlines and support circuit interconnect wiring are both formed from the same level of metal but they are patterned in separate masking steps. The stacked capacitors are separated from each other by less than the minimum dimension of the photolithographic system used for fabrication.

DRAM cell with stacked capacitor self-aligned to bitline

A computer graphics and display system is provided, comprising (i) a graphics system for outputting a first plurality of digital color signals; (ii) a first digital-to-analog converter (DAC) for converting the first plurality of digital color signals into a second plurality of analog color signals, the second plurality being less in number than the first plurality; (iii) a first analog-to-digital converter (ADC) for reconverting the second plurality of analog color signals back to the first plurality of digital color signals; and (iv) an LCD display device for receiving the reconverted first plurality of digital color signals. The first and second DACs and the first and second ADCs are implemented within the same integrated circuit (IC) chip. The first plurality of digital color signals comprises red, blue and green even pixels and red, blue and green odd pixels. Each color for both even and odd pixels is encoded onto a single pair of the first DACs by interleaving same color pixels onto the single pair.

Method and system for multiplexing and demultiplexing video signals for

A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.

Method of making corner protected shallow trench field effect transistor

Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.

Method of making contacted body silicon-on-insulator field effect

Contacted body silicon-on-insulator field effect transistor

Corner protected shallow trench isolation device

A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).

Method of forming borderless contacts using a removable mandrel

The present invention relates to an apparatus for remotely detecting impedance adapted for use on a polishing machine wherein the end point of polishing for removing a surface layer during the processing of semiconductor substrates is detected. A first stationary coil having a high permeability core is wound having an air gap and an AC voltage is applied to the stationary coil to provide a magnetic flux in the air gap. A second coil is mounted for rotation on the polishing table, in a position to periodically pass through the air gap of the stationary coil as the table rotates. The second coil is connected at its opposite ends to contacts which are embedded in the surface of the polishing wheel. The contacts are positioned to engage the surface of the substrate being polished and provide a load on the second rotating coil when it is in the air gap of the stationary coil, will perturb the flux field therein as a function of the resistance of the load caused by the contacts contacting either a conducting surface or a non-conducting surface. This perturbance of the flux field is measured as a change in the induced voltage in the stationary coil which is converted to a signal processed to indicate the end point of polishing, the end point being when a metallic layer has been removed to expose a dielectric layer or when a dielectric layer has been removed to expose a metallic layer.

Device for detecting an end point in polishing operations

The present invention relates to a method and apparatus for remotely detecting impedance. It is specifically adapted for use on a polishing machine wherein the end point of polishing for removing a surface layer during the processing of semiconductor substrates is detected. A first, or stationary coil having a high permeability core is wound having an air gap and an AC voltage is applied to the stationary coil to provide a magnetic flux in the air gap. A second coil is mounted for rotation on the polishing table, in a position to periodically pass through the air gap of the stationary coil as the table rotates. The second coil is connected at its opposite ends to contacts which are embedded in the surface of the polishing wheel. The contacts are positioned to engage the surface of the substrate which is being polished and provide a load on the second or rotating coil. The rotating coil, when it is in the air gap of the stationary coil, will perturb the flux field therein as a function of the resistance of the load caused by the contacts contacting either a conducting surface or a non-conducting surface. This perturbance of the flux field is measured as a change in the induced voltage in the stationary coil which in turn is converted to a signal which is processed to indicate the end point of polishing, the end point being when a metallic layer has been removed to expose a dielectric layer therebeneath or, conversely, when a dielectric layer has been removed to expose a metallic layer therebeneath.

Device and method for detecting an end point in polishing operation

A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrate. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.4, to provide a planarized upper surface of SiO.sub.2 and Si.sub.3 N.sub.4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.

Forming wide dielectric-filled isolation trenches in semi-conductors

Method of measuring changes in impedance of a variable impedance load by

A method of forming a bridge contact between a source diffusion region of a transfer gate FET and a polysilicon-filled trench storage capacitor electrodes of the FET. A layer of titanium is evaporated at a temperature of approximately 370.degree. C., so that the titanium has a substantially columnar grain structure and a minimum of matrix material. The bottom portions of the columnar grains have a lateral length that approximates the lateral length of the dielectric separating the source diffusion from the poly-filled trench. Thus, upon sintering at 700.degree. C. in an N.sub.2 atmosphere, titanium silicide will form over all exposed silicon regions as well as the dielectric, without shorting the FET electrodes together.

Silicide bridge contact process

A polishing tool for abrasively polishing a semiconductor wafer that edge clamps the wafer between two rollers. The wafer is spun-up in one plane and the rollers spin in a second plane which is orthogonal to the wafer spin plane. One of the rollers is split with each section rotating in opposite directions. Each of the rollers is mounted by a spring-gimballed assembly to follow the wafer contour.

System for mechanical planarization

A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor formed in monocrystalline silicon stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.

Growing community of inventors

Burlington, VT, United States of America

Brian J Machesney