Micron Technology Incorporated

Brian J Ladner

Daniel B Penney

Timothy B Cowles

Danial S Dean

Frank Alejano

Paul M Prew

Todd A Merritt

Sujeet V Ayyapureddi

Matthew Alan Prather

Scott Eugene Smith

Parthasarathy Gajapathy

Thanh K Mai

Randy Brian Drake

Todd A Merrit

The systems and methods described herein relate to a bi-directional data path (DQ) symbol map generated based on error correction operations. A device may include sub-wordline drivers and bi-directional data paths (DQs) that couple between the sub-wordline drivers and input/output (I/O) interface circuitry based on assignments indicated by the DQ symbol map. The assignments may be generated based on error correction operations performed on data of the memory bank. In particular, the DQ symbol map may be generated to avoid some conditions that, if occurring, may render one or more data errors uncorrectable. These systems and methods may reduce a likelihood of a data error associated with a DQ being uncorrectable.

Routing assignments based on error correction capabilities

A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

DDR5 four-phase generator with improved metastability resistance

Systems and methods may involve circuitry that receives a first transition of a clocking signal. The circuitry may also to enable a compensation circuit characterized by a capacitance in response to the first transition of the clocking signal and may receive subsequent transitions of the clocking signal. The circuitry may also apply the capacitance to the subsequent transitions of the clocking signal after enabling the compensation circuit to generate a compensated clocking signal characterized by an adjusted duty cycle relative to a duty cycle of the clocking signal.

Capacitance-based compensation circuitry

A method, apparatus, and system are provided for implementing a zero-enabled fuse system. An apparatus includes a first set of fuses for activating a first memory portion, and a second set of fuses for activating a second memory portion. The apparatus also includes a controller to control an operation of the first and second set of fuses. The controller is adapted to determine whether a zero address memory location relating to the first memory portion is to be activated based upon an enable fuse. The controller is adapted to also perform a check to determine whether the second set of fuses has been previously activated.

Zero-enabled fuse-set

A method and apparatus for programmable column segmentation of a memory device is disclosed. The method and apparatus provide different programmable selected column segmentation arrangements to provide more flexibility in primary column repair of a memory device.

Memory device having programmable column segmentation to increase flexibility in bit repair

Growing community of inventors

Plano, TX, United States of America

Brian J Ladner