Intel Corporation

Other

Brian Holscher

John W Horrigan

Namasivayam Thangavelu

George Vargese

Guillermo Juan Rozas

David A Dunn

James Van Zoeren

James A Wilson

Dean Gaudet

Jeffrey R Jones

A request tracking data prefetch apparatus for a computer system is described. The apparatus includes a prefetcher coupled to a memory of the computer system. A tracker is coupled to the prefetcher, and is configured to recognize an access to a plurality of cache lines of the memory by a processor of the computer system. A cache memory is coupled to the prefetcher. The prefetcher predictively loads a target cache line of the memory into the cache memory. The target cache line for the predictive load is indicated by the tracker.

Request tracking data prefetcher apparatus

Systems and methods for reordering processor instructions. In accordance with a first embodiment of the present invention, a microprocessor comprises circuitry to process an instruction extension, wherein the instruction extension is transparent to the programming model of the microprocessor. The instruction extension may comprise a field for indicating an offset from a memory structure pointer. The microprocessor includes circuitry for adding the offset to the memory structure pointer to indicate a specific element of the memory structure. The specific element of the memory structure comprises address information corresponding to speculative data.

Systems and methods for reordering processor instructions

Portions of a cache are flushed in stages. An exemplary flushing of the present invention comprises flushing a first portion, performing operations other than a flush, and then flushing a second portion of the cache. The first portion may be disabled after it is flushed. The cache may be functionally divided into portions prior to a flush, or the portions may be determined in part by an abort signal. The operations may access either the cache or the memory. The operations may involve direct memory access or interrupt servicing.

Cache flushing

An apparatus and method for selecting a next available buffer from among an array of buffers using a reduced count of logic gates. The apparatus includes an array of computational cells coupled to one another in a cascaded fashion, wherein each computational cell corresponds to a respective buffer in the array of buffers. The array of computational cells includes a first set of inputs for receiving data in accord with an availability vector comprising 1 bit for each buffer that identifies which buffers are available for allocation. A second set of inputs in accord with a current selected entry vector is also provided, wherein the current selected entry vector includes a single asserted bit that identifies that last buffer to be allocated. A computational cell includes logic to implement a pair of predefined logic equations, whereby a next available vector in accord with a first set of outputs on the array of computational cells. The next available vector comprises a single asserted bit that identifies a next available buffer to be allocated for use by apparatus, such as microprocessors, in which the invention is implemented.

Next available buffer allocation circuit

A computer processor includes a dynamic latency module. The dynamic latency module includes a read-only memory ('ROM') in which is stored a plurality of sets of latency values. The dynamic latency module further includes a register coupled to the ROM and adapted to store at least one set of the plurality of sets of latency values. The dynamic latency module dynamically sets a plurality of memory access latency values by determining an operating speed of the processor and implementing one of the plurality of sets of latency values based on the operating speed.

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Hillsboro, OR, United States of America

Brian Holscher