Siliconix Incorporated

Aptus Power Semiconductor

Fairchild Semiconductor Corporation

Impala Linear Corporation

Other

Power Integrations, Inc.

Aptus Power Semiconductors

Brian Harold Floyd

Mike F Chang

Fwu-Iuan Hshieh

Richard Kent Williams

Mohamed N Darwish

Shekar Mallikarjunaswamy

Daniel Ng

Wayne Bryan Grabowski

Dorman C Pitzer

Andreas Volke

Christoph Dustert

Brian Cheung

Min Juang

Chin H Ho

Karen Lee

Danny Nim

A switched inductive storage element to enhance gate drive at turn-off is described herein. An inductive storage element (e.g., an inductor) may be switched between a supply node and a gate node of a gated device (e.g., a low-side device and/or a high-side device). While coupled to the supply node, the inductive storage element may be energized; and subsequently, while coupled to the gate node of the gated device, the inductive storage element may drive the gate node (i.e., the gate of the low-side and/or high-side device) below the local ground potential.

Switched inductive storage element to enhance gate drive at turn-off

Provided herein are apparatus and methods for low voltage high power supply rejection ratio (PSRR) systems. A charge pump converts a supply voltage to a larger charge pump voltage and provides the charge pump voltage to a circuit subsystem. The charge pump voltage is regulated to a state dependent reference. In the steady state the charge pump voltage is regulated with respect to an output voltage of the circuit subsystem; in this way PSRR of the circuit subsystem is enhanced.

Apparatus and methods for low voltage high PSRR systems

A charge pump comprises, a plurality of branches each having serially-connected T-circuit cells, wherein each of the branches has a first end for receiving an input voltage and a second end for outputting a charge pump voltage, wherein each of the T-circuit cells comprises a first transistor, a second transistor, and a capacitor, wherein the first transistor and the second transistor of each of the T-circuit cells have a common drain, and wherein the gate of the first transistor of a certain one of the T-circuit cells of a certain branch is connected to a first branch and the gate of the second transistor of the certain one of the T-circuit cells of the certain branch is connected to a second branch.

Methods and circuits for a low input voltage charge pump

A method for operating a load switch, wherein a charge pump drives a gate of the load switch, comprises the steps of: controlling a charge pump frequency as a function of states of the load switch; generating a charge pump output as a function of the charge pump frequency; and providing the charge pump output to the gate of the load switch.

Load switch system driven by a charge pump

A temperature stable comparator circuit, comprised of: a branch C having a first end, a second end, a first type-device and first type-device, wherein the first type-device and the first type-device are connected to a node O; a branch B having a first end, a second end, a second type-device, a second type-device, and a resistor; and a branch A having a first end, a second end, a third type-device and a current-control device; wherein the first ends of the branch A, branch B, and branch C are commonly connected, and the second ends of the branch B and branch C are commonly connected.

Temperature-stable CMOS voltage reference circuits

A charge pump circuit comprises a plurality of subcircuits, where the subcircuits are connected to each other in a single or a dual array having a repeating pattern. Each of the subcircuits comprises one or more of the following: an X-channel device having an X-gate terminal, an X-source terminal and an X-drain terminal, a Y-channel device having a Y-gate terminal, a Y-source terminal and a Y-drain terminal, and a capacitor; wherein a first end of the capacitor, the X-drain terminal, and the Y-drain terminal are connected with each other to form the common drain terminal; and wherein a second end of the capacitor is the clock terminal.

A voltage comparator, comprises: a first branch comprising a first transistor, a first resistor (R), and a first current dependent voltage source (VA), wherein a first voltage (V) is applied across the first branch to generate a first current and wherein the first transistor is a diode-connected transistor; a second branch comprising a second resistor (R), a second current dependent voltage source (VB), and a second transistor having a control voltage (V), wherein a second voltage (V) is applied on an end of the second branch to generate a second current; and a third branch for generating a comparator output, wherein a trip point of the comparator output is set to when the first current and the second current are equal and wherein the trip point is a function of the transistors, the resistors, and the current dependent voltage sources of the first branch and the second branch.

Voltage comparators

In an embodiment, a charge pump of relatively simple design is provided which can generate sufficient drive voltage for a power switching device from a low-supply-voltage (e.g., 1V). In some embodiments, this charge pump performs better at lower input voltages when there are loading conditions (i.e., when the charge-pump output powers other circuit blocks such as amplifiers and LDO's).

Low-input-voltage charge pump

In one embodiment, an integrated circuit is provided for detecting when a temperature reaches a specified value. The circuit includes a differential circuit block having first and second transistors. A control terminal of the first transistor is coupled to a first voltage source, and a control terminal of the second transistor is coupled to a second voltage source. The second transistor has an area larger than the first transistor. The differential circuit block compares a first current flowing into the first transistor and a second current flowing into the second transistor. The differential circuit block outputs a signal to indicate that the specified temperature has been reached when the first current equals the second current according to specified values of the first voltage source, the second voltage source, and the ratio of the areas of the first and second transistors. A single-ended circuit block amplifies the output signal of the differential circuit block to a predetermined amplitude.

Process-invariant low-quiescent temperature detection circuit

In one embodiment, a charge pump system includes an input terminal at which an input voltage is received, and an output terminal at which at an output voltage is provided. N stages are connected in cascade between the input terminal and the output terminal. Each of the N stages includes at most one inverter circuit, the inverter circuit having a first transistor connected at a node to a second transistor. A first capacitor is coupled at one end to the node between the first and second transistors, and is coupled at another end to receive one of two non-overlapping phase signals. In each stage, at one value for the one of two non-overlapping phase signals, the first capacitor of the stage is charged by a respective stage input voltage, and at another value for the one of two non-overlapping phase signals the first capacitor of the stage is discharged to provide a respective stage output voltage. The charge pump system is capable of generating the output voltage with a greater magnitude than the input voltage even when the supply voltage is relatively low, e.g., below 1V.

A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

Method of operation of punch-through field effect transistor

A current-limit circuit and a method of limiting current supplied to a load through a power transistor utilize a control transistor that is selectively activated to a conducting state to limit the current conducted through the power transistor in response to a predefined condition. The predefined condition may be a short-circuit condition or an over-current condition. The configuration and operation of the control transistor are such that, when the control transistor is in a conducting state, the current conducted through the power transistor is limited by the structural ratio of the two transistors. However, during normal operating conditions when the control transistor is deactivated to a non-conducting state, the control transistor does not degrade the performance of the power transistor. In a first embodiment, the current-limit circuit is configured to provide protection from a short-circuit condition. In a second embodiment, the current-limit circuit is configured to provide protection from an over-current condition, in addition to protection from a short-circuit condition. In a preferred embodiment, the sense transistor and the power transistor are structurally integrated into a single semiconductor device having a honeycomb structure that allows the size of the sense transistor to be tuned.

Short-circuit current-limit circuit

A circuit and a method for comparing an input voltage to an internally generated reference voltage utilize a bias network to make the voltage comparison. The bias network is preferably configured to generate a proportional-to-absolute-temperature (PTAT) reference voltage, which is used for the voltage comparison. Although the circuit can be implemented to operate in a number of applications, the circuit is particularly useful in a current sensing application. The circuit includes the bias network, a comparison current path and an output terminal. The comparison current path is configured to partially duplicate a current path of the bias network on which the reference voltage is generated. The comparison current path includes a current control element and an active transistor. Depending on the input voltage applied to the active transistor of the comparison current path, the output terminal is driven to generate either a high or a low comparison signal. In a first embodiment, the circuit is configured to sense voltages near the supply voltage. In a second embodiment, the circuit is configured to sense voltages near the electrical ground. In either embodiments, the circuit requires a startup circuit to initiate the bias network into a conducting state.

Low level input voltage comparator

In the present method, a semiconductor substrate is provided with an epitaxial layer thereon. A source/drain region is provided in a portion of the epitaxial layer, and a plurality of trenches are etched in the epitaxial layer and extend into the substrate, to define a plurality of mesas. An oxide layer of generally uniform thickness is provided over the mesas and in the trenches, and a polysilicon layer is provided over the oxide layer and is etched so that the oxide layer overlying the mesas is exposed, and the top surface of the polysilicon within the trenches is below the level of the tops of the mesas. A layer of spin-on-glass (SOG) is provided, and the SOG layer and oxide layer are etched substantially to the level of the tops of the mesas, to expose the tops of the mesas and to leave the portions of the SOG over the respective polysilicon portions in the trenches substantially coplaner with the tops of the mesas. A conductive layer is provided over the remaining portions of the SOG layer and the tops of the mesas.

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Sunnyvale, CA, United States of America

Brian Harold Floyd