Texas Instruments Corporation

Brian Goodlin

Bhaskar Srinivasan

Ricky A Jackson

Walter Baker Meinel

Stuart M Jacobsen

Kalin Valeriev Lazarov

Nicholas Stephen Dellas

Benjamin Stassen Cook

Kurt Peter Wachtler

Genki Yano

Makoto Yoshino

Karen Kirmse

Ayumu Kuroda

Haowen Bu

Mona M Eissa

Ting-Ta Yen

Amitava Chatterjee

Thomas Dyer Bonifield

Honglin Guo

Joe W McPherson

Pushpa Mahalingam

Neng Jiang

Umamaheswari Aghoram

Jong Shik Yoon

Shirin Siddiqui

Karen H R Kirmse

Maciej Blasiak

Qidu Jiang

Erich Wesley Kinder

Dongmei Lei

Mark R Visokay

Marie Denison

Alexei Sadovnikov

Manoj K Jain

Wei-Yan Shih

Ming-Yeh Chuang

Asad Mahmood Haider

Lance W Barron

Dhishan Kande

Alan G Merriam

Eric H Warninghoff

Roger Charles McDermott

Iqbal R Saraf

Walter Scott Idol

A method forms a semiconductor device with a substrate including semiconductor material formed to include plural corrugation members, each member including a top surface, and a first and second sidewall extending from the top surface to a lower surface. The method forms a contiguous transistor source extending through a first volume of each of the corrugation members and a first lower surface volume and a contiguous transistor drain extending through a second volume of each of the corrugation members and a second lower surface volume. Both source and drain are formed by initially diffusing a dopant in a uniform manner normal to various portions, some non-coplanar, of the source and drain, respectively.

Corrugated metal oxide semiconductor transistor

A fin field-effect transistor ('FinFET') semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

Fin field-effect transistor semiconductor device and method of forming the same

An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.

IC having trench-based metal-insulator-metal capacitor

A packaged micro-electro-mechanical system (MEMS) device () comprises a circuitry chip () attached to the pad () of a substrate with leads (), and a MEMS () vertically attached to the chip surface by a layer () of low modulus silicone compound. On the chip surface, the MEMS device is surrounded by a polyimide ring () with a surface phobic to silicone compounds. A dome-shaped glob () of cured low modulus silicone material covers the MEMS and the MEMS terminal bonding wire spans (); the glob is restricted to the chip surface area inside the polyimide ring and has a surface non-adhesive to epoxy-based molding compounds. A package () of polymeric molding compound encapsulates the vertical assembly of the glob embedding the MEMS, the circuitry chip, and portions of the substrate; the molding compound is non-adhering to the glob surface yet adhering to all other surfaces.

Structures for packaging stress-sensitive micro-electro-mechanical system stacked onto electronic circuit chip

A micromechanical system (MEMS) acoustic wave resonator is formed on a base substrate. A piezoelectric member is mounted on the base substrate. The piezoelectric member has a first electrode covering a first surface of the piezoelectric member and a second electrode covering a second surface of the piezoelectric member opposite the first electrode, the second electrode being bounded by a perimeter edge. A first guard ring is positioned on the second electrode spaced apart from the perimeter edge of the second electrode.

Buk acoustic wave resonator with guard rings having recessed space from electrode edge and periodic designs

A method for creating a double Bragg mirror is provided. The method comprises providing a wafer having a plurality of bulk acoustic wave (BAW) devices at an intermediate stage of manufacturing. A first dielectric layer is deposited over the wafer. A plurality of as-deposited thicknesses of the dielectric layer are determined, each as-deposited thickness corresponding to one BAW device from the plurality of BAW devices. A corresponding trimmed dielectric layer over each of the BAW devices is formed by removing a portion of the dielectric layer over each of the BAW devices, with a thickness of the removed portion determined from a corresponding as-deposited thickness and a target thickness. A Bragg acoustic reflector that includes the corresponding trimmed dielectric layer is formed over each of the BAW devices.

Method for creating double bragg mirror for tight frequency reference control

An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

An electronic device comprises: a molybdenum layer; a bond pad formed on the molybdenum layer, the bond pad comprising aluminum; and a wire bonded to the bond pad, the wire comprising gold.

Electronic devices with bond pads formed on a molybdenum layer

A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer comprising an unpatterned resistive layer. Measurements are obtained of a characteristic of the unpatterned resistive layer at each of a plurality of locations over the substrate. The unpatterned resistive layer is modified, such as by targeted removal of layer material, in response to the measurements such that the measured characteristic is more uniform across the substrate. A resistor on the IC is defined from the unpatterned resistive layer after the modifying.

IC with ion milled thin-film resistors

In described examples of a micromechanical system (MEMS), a rigid cantilevered platform is formed on a base substrate. The cantilevered platform is anchored to the base substrate by only a single anchor point. A MEMS resonator is formed on the cantilevered platform.

Bulk acoustic wave resonator on a stress isolated platform

A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the cavity. The sealing layer is may include a photosensitive material, and the sealing layer may be patterned using a photolithographic process to form an IR-absorbing seal. Alternately, the sealing layer may be patterned using a mask and etch process to form the IR-absorbing seal.

Infrared sensor design using an epoxy film as an infrared absorption layer

A bulk acoustic wave (BAW) resonator includes a substrate having a top side surface and a bottom side surface. A Bragg mirror is on the top side surface of the substrate. A bottom electrode layer is on the Bragg mirror, and a piezoelectric layer is on the bottom electrode layer. A top dielectric layer is on the piezoelectric layer, and a top electrode layer is on the top dielectric layer. The bottom side surface of the substrate has a surface roughness of at least 1 &#x3bc;m root mean square (RMS).

Bulk acoustic wave (BAW) device having roughened bottom side

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Brian Goodlin