International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Brian Gerard Holthaus

Jonathan Louis Kaus

Eric G Thiemann

Robert W Todd

Ronald Leroy Billau

David R Engebretsen

David Lee Dosch

Daniel Frank Moertl

Charles Scott Graham

Ellen Marie Bauman

Paul Edward Movall

Neil Clair Berglund

Roger John Gravrok

Thomas James Osten

Daniel Robert Lipps

Frederick J Ziecina

Daniel Paul Wetzel

Scott J Timmerman

Darryl Solie

Brent R Inches

A management controller in a distributed network switch may operate on sets of ports such that sets of ports containing a same port are processed serially, and sets that do not contain any of the same ports can be processed in parallel. When receiving a set of ports for processing, the management controller organizes the ports into lanes that each correspond to a unique port. If any of the lanes overlap, subsequent port sets are blocked from proceeding until the lanes of preceding port sets are cleared. If no lanes overlap, the sets may be deemed disjoint, and subsequent port sets may be processed in parallel.

Selective locking of operations on joint and disjoint sets

An electronic system having a high speed signaling bus requiring training (calibration) of a calibrated item in a driver circuitry or a receiver circuitry for reliable operation. At manufacturing or in a secure location, secure calibration coefficients are determined for the electronic system and are stored in a non-volatile storage. During operation, the high speed signaling bus may be re-calibrated, resulting in a new currently active calibration coefficient for the calibrated item. A coefficient watchdog checks a new coefficient value selected by the re-calibration at present environmental conditions such as voltage and temperature against the secure calibration coefficients. If the new calibration coefficient value is the same as a calibration coefficient value in an acceptably close secure calibration coefficient, the new calibration coefficient is accepted; if not, a potentially probed warning is created by the coefficient watchdog.

Snoop detection on calibrated bus

Techniques are disclosed to perform an operation to facilitate concurrent repair of PCIe switch units in processing environments such as a tightly coupled, multi-switch, multi-adapter, multi-host distributed system. The operation, for an identified switch unit to be repaired, reconfigures all switch unit hardware in the switch fabric by removing all upstream to downstream connections utilizing the identified switch unit. Connections to hosts via the upstream ports are also removed by the operation. Once the switch unit is powered back on, the operation reconfigures all switch unit hardware in the switch fabric by adding all upstream to downstream connections utilizing the identified switch unit. The operation further restores connections to hosts via the upstream ports.

Concurrent repair of PCIE switch units in a tightly-coupled, multi-switch, multi-adapter, multi-host distributed system

Concurrent repair of the PCIe switch units in a tightly-coupled, multi-switch, multi-adapter, multi-host distributed system

A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus. The original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (&plus;X1, &plus;X2, or &plus;X3) for shifting the original address above a predefined boundary for each originator/target of the operation. Shifting back the shifted address to the original address for completing the operation on the destination bus uses a respective predefined value (&minus;X1, &minus;X2, or &minus;X3) for the shifted back address to the original address for completing the operation on the destination bus. Using the shifted address on the single bus utilizes a dual address cycle (DAC) of the single bus for the shifted address. Completing the operation on a destination bus utilizes a single address cycle (SAC) of the destination bus for the shifted back address to the original address.

Method of mapping multiple address spaces into single PCI bus

An adapter node is provided for use in adapting internal system enclosure services to a system power control network to thereby provide remote power control, diagnostics, and logical-to-physical correlation information, through the system power control network. The adapter node is for use in one computer of a plurality of different types of computers, having a respective internal system enclosure services low-level communication path. The power control network has a plurality of nodes, one of the nodes being a control node. The adapter node includes a substrate having electrical contacts adapted to plug to a system bus in the one computer. The substrate further has at least one system enclosure services interface connection to connect to the internal system enclosure services low-level communication path in the one computer. The adapter node further has a system power control network interface connection for connecting to the system power control network. A processor of the adapter node is provided for coordinating communication with the system power control network and with internal devices on the internal system enclosure services low-level communications path. Power control, diagnostics, and logical-to-physical correlation information signals are communicated between the system power control system control node and the adapter node to provide system enclosure services support to the one computer of the plurality of different types of computers.

Heterogeneous system enclosure services connection

Growing community of inventors

Oronoco, MN, United States of America

Brian Gerard Holthaus