Motorola Corporation

Nxp Usa, Inc.

Brian George Anthony

Suresh Venkatesan

Janos Farkas

Venkat Kolagunta

Mohammed Rabiul Islam

Rajesh Tiwari

John Mendonca

Abbas Guvenilir

Olubunmi O Adetutu

Douglas Michael Reber

William Ernest Edwards

Alexander Barr

Bradley Paul Smith

Sam S Garcia

Dean J Denning

Stuart E Greer

Ramnath Venkatraman

David Clegg

Gregor Braeckelmann

Gregory Norman Hamilton

Stephen R Crown

Rebecca G Cole

Daniel J Loop

Md Rabiul Islam

A method of protecting a dielectric during fabrication is provided. A conductive layer is patterned to form a first conductive shape on a first portion of a dielectric layer and a second conductive shape on a second portion of the dielectric layer. A conductive trace is formed over at least a portion of the second conductive shape. The conductive trace electrically connects the first conductive shape with a substrate tie. An interconnect layer is coupled to the first conductive shape. The conductive trace is etched to electrically isolate the first conductive shape from the substrate tie.

In-line protection from process induced dielectric damage

An interconnect overlies a semiconductor device substrate ( ). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer ( ) overlies the conductive barrier layer and the passivation layer ( ) has an opening that exposes portions of the conductive barrier layer ( ). In an alternate embodiment a passivation layer ( ) overlies the interconnect, the passivation layer ( ) has an opening ( ) that exposes the interconnect and a conductive barrier layer ( ) overlies the interconnect within the opening ( ).

Method of forming semiconductor device including interconnect barrier layers

A copper interconnect polishing process begins by polishing ( ) a bulk thickness of copper ( ) using a first platen. A second platen is then used to remove ( ) a thin remaining interfacial copper layer to expose a barrier film ( ). Computer control ( ) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed ( ) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier ( ) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations ( ). A scrubbing operation ( ) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process

A method for forming an improved copper inlaid interconnect (FIG. ) begins by performing an RF preclean operation ( ) on the inlaid structure in a chamber ( ). The RF preclean rounds corners ( and ) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces ( ). A tantalum barrier ( ) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer ( ), a copper seed layer ( ) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp ( ) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

Method of forming a semiconductor device barrier layer

A copper interconnect polishing process begins by polishing (,) a bulk thickness of copper (,) using a first platen. A second platen is then used to remove (,) a thin remaining interfacial copper layer to expose a barrier film (,). Computer control (,) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (,) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (,) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (,). A scrubbing operation (,) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.

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Austin, TX, United States of America

Brian George Anthony