Xilinx, Inc.

Triscend Corporation

Tabula, Inc.

Altera Corporation

Brian Fox

Andreas Papaliolios

Steven Winegarden

Sridhar Krishnamurthy

Jean-Didier Allegrucci

Bart Reynolds

Edmond Y Cheung

Fung Fung Lee

Wilson Kaming Yee

Arye Ziklik

Danesh Tavana

Stanley S Yang

A method for testing a set of circuitry in an integrated circuit (IC) is described. The IC includes multiple configurable circuits for configurably performing multiple operations. The method configures the IC to operate in a user mode with a set of test paths that satisfies a set of evaluation criteria. Each test path includes a controllable storage element for controllably storing a signal that the storage element receives. The method operates the IC in user mode. The method reads the values stored in the storage elements to determine whether the set of circuitry is operating within specified performance limits.

Micro-granular delay testing of configurable ICs

The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The present invention also provides certain features, transparent to the user, which optimize system resources and ensure the correct initialization of the CSoC. The CSoC leverages an on-chip central processing unit (CPU) to control the configuration process of the configurable system logic (CSL). Advantageously, the CSL configuration memory cells as well as other programmable locations in the CSoC are addressable as part of a system bus address space. The system bus is a multi-use structure that can be used for both configuring and reading of memory cells. In this manner, the CSoC optimizes system resources.

Configuration in a configurable system on a chip

A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.

Method and apparatus to facilitate self-testing of a system on chip

The I/O circuit of the present invention provides optimal flexibility and performance using a number of different structures and methods. The present invention provides a signal follower circuit for an input pad. In one embodiment, the output buffer is capable of injecting a constant onto a pad during reconfiguration of a configurable system logic circuit. The present invention also provides a circuit for generating a programmable data propagation delay, thereby guaranteeing zero hold time for an arbitrary input register. Zero hold time is accomplished by allowing the user to optimally characterize clock delay to a given input/output circuit. The present invention also provides fast switching between input pads, thereby minimizing data propagation delay between the input pads. Additionally, the present invention reduces time spent in production product test by facilitating the testing of multiple routes with one test configuration. A circuit expanding the number of data input channels available to system routing is provided. Lastly, a plurality of identical input/output block tiles (IOBTs) is disclosed, thereby enabling each I/O circuit to provide the same signals regardless of the IOBTs location in the I/O circuit.

Input/output circuit with user programmable functions

Method and apparatus to facilitate self-testing of a system on a chip

Interface logic is disclosed. The interface logic comprises a first address decoder, a first set of mode logic coupled to the address decoder and a first selector coupled to the first set of mode logic. The interface logic is adaptable to connect the programmable logic to the system interconnect via one of a plurality of access modes supported by the system interconnect.

Programmable interface for a configurable system bus

A programmable input/output memory architecture. The programmable input/output memory cells are disposed in two segments about the periphery of the chip. Each segment has two data buses for separate reading and writing of the configuration register. Each cell is selected and configured according to user specifications. Corresponding memory cells from each segment share the same select line, therefore two bytes of configuration data are accessed together and the data is propagated through both segments approximately concurrently thereby reducing propagation delay.

Input/output architecture for efficient configuration of programmable input/output cells

The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

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Sunnyvale, CA, United States of America

Brian Fox