Illumina Corporation

Illumina Singapore Pte. Ltd.

Pacific Data Products, Inc.

Brian Elliot Sinofsky

Kirkpatrick W Norton

Soham Sheth

Lea Kobeli

Erik Allegoren

Scott Michael Janis

Beng Keong Ang

Anna Skaro Quackenbush

Michael Justin Wright

Yulin Ye

Jay T Flatley

Voon Yeow Seng

Lim Peng Huay

Fred Lundquist

Cliff Quayle

Low Hong Yeap

A method comprises: accessing animation graphics files and a mask graphics file; generating first binary sequences corresponding to the animation graphics files, and generating a second binary sequence corresponding to the mask graphics file; and outputting the first binary sequences and the second binary sequence to hardware controlling an array of electrical components.

Controlling electrical components using graphics files

LED board interconnect schemes for illuminable assemblies are provided. Multiple LED boards may form a partial perimeter along an illuminable assembly. The multiple LED boards and interconnects must fit within a limited width and height of the illuminable assembly. In some implementations, an interconnect board and spring connectors are used to provide a low-profile electrical interconnection while maintaining co-planarity of the LEDs across the LED boards.

PCB interconnect scheme for co-planar LED strips

Sequencing or sample preparation instrument

A method for increasing the addressable memory space of an addressed line limited computer system. In the present invention, at least two memory planes, plane zero and plane one, are provided. Each memory plane contains the maximum number of addresses that can be addressed by the available address lines. The present invention constrains the starting addresses of individual character data that are valid in each memory plane. For example, if the addresses of the memory planes are configured in hexidecimal, memory plane zero contains valid starting addresses only at those locations having a least significant nibble of zero or eight. Memory plane one is constrained to have valid starting addresses, for example, at those addresses having a least significant nibble of '4' or 'C'. A processing means is provided to determine when a starting address is provided to the memory. The processor determines which memory plane can accept the starting address as a valid starting address and enables the address lines to communicate with that memory plane. More memory planes can be defined by reviewing more bits in the starting address. For example, if two bits are reviewed, four memory planes can be defined. For a given number of address lines N reviewed, the maximum number of memory planes is 2.sup.N.

Memory addressing scheme

Growing community of inventors

San Diego, CA, United States of America

Brian Elliot Sinofsky