Texas Instruments Corporation

Brian E Zinn

Jonathan Philip Davis

Fuchao Wang

Neal T Murphy

Yousong Zhang

Andrew Frank Burnett

Mona M Eissa

Barry Lanier

An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.

Magnetic core for integrated magnetic devices

Method to form magnetic core for integrated magnetic devices

A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond.

Method to improve CMP scratch resistance for non planar surfaces

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads.

Bond pad having ruthenium directly on passivation sidewall

A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium removal rate of at least 80 nanometers per minute at a polish pad pressure less than 9 psi and a surface speed between 1.9 and 2.2 meters per second. The palladium CMP operation may be applied to form a palladium bond pad cap after which an external bond element is formed on the palladium bond pad cap. Alternatively, the palladium CMP operation may be applied to form a palladium interconnect conductor in a first dielectric layer.

Aluminum enhanced palladium CMP process

Light is incident on a semiconductor wafer polish surface and an adjacent reference surface (). The reflected light from each surface is detected by a detector () positioned beneath the surfaces. The signals derived from each source of reflected light is analyzed in a electronic system () and an endpoint for a chemical mechanical polish process is determined as a function of both signals.

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Plano, TX, United States of America

Brian E Zinn