Pdf Solutions, Incorporated

Brian E Stine

Dennis Ciplickas

Christopher Hess

Larg H Weiland

Sherry F Lee

John Kibarian

David M Stashower

Kimon Michaels

Purnendu K Mozumder

Joseph C Davis

Richard Gene Burch

Stefano Tonello

Jeffrey Drue David

Rakesh Vallishayee

Kurt H Weiner

Ratibor Radojcic

Lin Lee Cheong

Tomonori Honda

Qing Zhu

Carlo Guardiani

Michael Keleher

Guanyuan Michael Yu

Senthil Arthanari

Spencer B Graves

Michel Quarantelli

Joshi Aniruddha

Yanwen Fei

Markus Decker

Nicola Dragone

Mark Zwald

Said Akar

Vaishnavi Reddipalli

Nobuchika Akiya

Anand Inani

Lijin Zhu

Marci Yi-Ting Liao

Michael V Williamson

Kenneth Harris

Joe Davis

Enrico Malavasi

Abdulmobeen Mohammad

Victor Kitch

Stefano Zanella

Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.

Collaborative learning model for semiconductor applications

A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.

Characterization vehicles for printed circuit board and system design

Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones. Described further is an system and method for implementing a heuristic mapping of trace data for distinguishing between good or bad traces in an Internet-based or offline application. The result of this detection can then be used for yield improvement or for burn-in reduction where for example burn-in chips having 'good' circuit traces are subjected to thermal stress for less time than for chips identified as having 'bad' circuit traces.

Failure detection for wire bonding in semiconductors

Described is a method of reducing multitudes of input data signals to a manageable plurality of input data signals and using the manageable plurality of input data signals to obtain response data that is provided to the semiconductor wafer, packaging, or design facility.

Advanced manufacturing insight system for semiconductor application

A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

Test cells for semiconductor yield improvement

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

System and method for product yield prediction

In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.

Identifying yield-relevant process parameters in integrated circuit device fabrication processes

An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.

Designing an integrated circuit to improve yield using a variant design element

A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb structure having a plurality of side walls. The tines of the first comb structure are positioned within side walls of the snake structure or second comb structure. The tines of the first comb structure are offset from a center of the side walls. Test data collected from the test structure are analyzed, to estimate product yield. The test structure may have a lower layer pattern, such that topographical variations of the lower layer pattern propagate to an upper layer pattern of the test structure.

Test structures and models for estimating the yield impact of dishing and/or voids

A method for improving yield of a process for fabricating a read-only memory (ROM) includes evaluating a yield of a ROM fabrication process associated with a first ROM design. At least two candidate ROM design modifications are identified. At least one of the candidate ROM design modifications comprises inversion of bit values of data to be stored in the ROM. A plurality of criteria are applied, including at least an amount of yield improvement and a difficulty of implementation associated with each candidate ROM design modification. One of the candidate ROM design modifications is selected based on the application of the criteria. A modified ROM fabrication process is performed to fabricate a ROM according to the selected ROM design modification.

Method and system for ROM coding to improve yield

A test structure combines a first structure () for erosion evaluation with a second structure () for extraction of defect size distributions. The first structure () is a loop structure usable determine a resistance value that varies with metal height. The second structure is a NEST structure (). Loop lines of the loop structure () are connected on both sides of the NEST structure ().

Test structures for estimating dishing and erosion effects in copper damascene technology

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Santa Clara, CA, United States of America

Brian E Stine