Lsi Logic Corporation

Lsi Corporation

Brian E Burdick

Edson Wayne Porter

Todd A Randazzo

Matthew S Von Thun

William K Petty

Gabriel Leandro Romero

Kevin J Bruno

Frederick G Smith

Stephen R Burnham

Driving multiple consecutive bits having a same logic value in a serial data stream involves driving a first bit of the multiple consecutive bits in the serial data stream at an initial voltage level, and driving at least two additional bits of the multiple consecutive bits in the serial data stream at voltage levels stepped down from the initial voltage level.

Driving multiple consecutive bits in a serial data stream at multiple voltage levels

An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.

Programmable transmit SCSI equalization

An apparatus comprising a device and a resistor. The device generally comprises (i) a gate configured to receive an input voltage, (ii) a drain coupled to a first supply voltage, and (iii) a source coupled to an output. The resistive element is generally coupled between the source and a second supply voltage. The apparatus generally provides voltage tolerance between the input voltage and the output.

Five volt tolerant and fail safe input scheme using source follower configuration

An apparatus having a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.

Multi-phase edge rate control for SCSI LVD

A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.

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Colorado Springs, CO, United States of America

Brian E Burdick