Silicon Laboratories Inc.

Cirrus Logic Inc.

Nxp B.v.

Crystal Semiconductor Corporation

Brian Douglas Green

Donald A Kerth

Lysander Lim

Srihari Adireddy

Michael R May

Javier Elenes

Augusto Manuel Marques

Ramkishore Ganti

Brian P Lum Shue Chan

Russell Croman

Scott Willingham

Tod Paulus

Jing Li

James P Maligeorgos

Thomas Glen Ragan

James Martin Nohrden

Kishore Ganti

Xiachuan Guo

A radio frequency (RF) signal is received in a receiver, and various counts based on information from the signal can be obtained. Counts of a number of samples of the RF signal exceeding first and second thresholds can be accumulated during an accumulation window. From the first of these counts, it can be determined if the count exceeds a first metric corresponding to a first predetermined count value, and if so, a gain of an RF gain element can be reduced. From the second of these counts it can be determined if this count exceeds a second metric corresponding to a second predetermined count value, and if not, the gain can be increased.

Statistical gain control in a receiver

In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.

Detecting digital radio signals

Techniques are disclosed relating to generating compatible clock signals. In one embodiment, an apparatus is configured to receive an input clock signal and a reference clock signal. In this embodiment, the apparatus includes a rate estimation unit and a phase-locked loop (PLL) unit. In this embodiment, the PLL unit is configured to generate, using a control signal from the rate estimation unit and the input clock signal, a PLL output clock signal. In this embodiment, the rate estimation unit is configured to adjust the control signal such that the PLL output clock signal and the reference clock signal are compatible. In this embodiment, the rate estimation unit is configured to adjust the control signal based on the reference clock signal and a comparison clock signal generated by the apparatus based on the PLL output clock signal.

Generating compatible clocking signals

A technique includes receiving data that is communicated in a frame over a wireless network and processing the data through a filter. A response of the filter is changed during the processing.

Filtering data in a wireless receiver system

A method and apparatus for adjusting a sample rate for an asynchronous sample rate converter is disclosed. In one embodiment, an apparatus includes an asynchronous sample rate converter (ASRC) that is configured to receive a digital data stream provided at a first sample rate. The ASRC is configured to convert the digital data stream to a second sample rate at which it is output. The apparatus also includes a sample rate estimator coupled to an interface through which samples from the digital data stream are conveyed subsequent to conversion to the second sample rate. The sample rate estimator is further coupled to the ASRC, and configured to adjust the second sample rate based on information obtained from the interface.

Sample rate estimator for digital radio reception systems

A receiver includes a memory, processing circuitry, and a memory protection unit. The processing circuitry is coupled to the memory, and has an input for receiving a radio frequency (RF) signal, and an output for providing an output signal at another frequency. The processing circuitry includes one or more independently powered components adapted to write data to the memory. The memory protection unit is coupled to the memory, and monitors a power supply voltage level corresponding to each independently powered component and, if the power supply voltage level changes during a power supply transition of an independently powered component in which the power supply voltage remains sufficiently large to power the independently powered component, to prevent write operations received from a corresponding one of the one or more independently powered components from occurring at least while the power supply voltage level is changing.

Receiver, system, and memory with memory protection during power supply transitions

In one embodiment, the present invention includes a transceiver coupled to a baseband processor to receive digital control information that includes both event and schedule information, and which stores the digital control information in a storage of the transceiver. The transceiver may then be operated according to the event and schedule information.

Digital interface and related event manager for integrated circuits

In one implementation, a method includes receiving control information in a transceiver from a baseband processor and computing ramp values in the transceiver based on the control information. The ramp values may be computed in a signal generator of the transceiver such as an algorithmic generator. Depending on mode of operation, the ramp values may be provided to a power amplifier or a gain block of the transceiver.

Autonomously generating ramp profiles in a transceiver

Image rejection factors are calibrated for a receiver circuit () during an initialization period. The image rejection factors are stored in a quasi non-volatile memory () associated with the receiver circuit (). The quasi non-volatile memory () is powered from a first source (VA) during a first receiver mode and from a second source (V) during a second receiver mode.

Quasi non-volatile memory for use in a receiver

In one embodiment, the present invention includes a method for receiving at a transceiver from a baseband processor digital control information that includes both event and schedule information, storing the digital control information in a storage of the transceiver, and operating the transceiver according to the event and schedule information.

A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined. When the receiver switches to a normal operating mode, the frequency synthesizer, ADCs and DSP are clocked by a main clock signal instead of the divided down test tone, and the test tone is removed from the mixers.

Wireless communication system and method using clock swapping during image rejection calibration

A technique includes forming a first well in a substrate and forming a second well in the substrate. The first well is electrically isolated from the second well. The technique includes forming an element in the second well to limit current between the first well and the substrate.

Integrated circuit having features to limit substrate current

A voltage regulator configured to receive a supply voltage from a voltage supply and provide a regulated voltage to digital circuitry is provided. The voltage regulator comprises first circuitry configured to inhibit high frequency energy generated by the digital circuitry from transmitting into the voltage supply, second circuitry configured to inhibit low frequency energy generated by the digital circuitry from transmitting into the voltage supply, and third circuitry configured to maintain the regulated voltage at a substantially constant value in response to a current drawn by the digital circuitry.

Growing community of inventors

Austin, TX, United States of America

Brian Douglas Green