Lightfleet Corporation

Xyron Corporation

Mcvan Aerospace

Brian Donovan

William B Dress

Ray S McKaig

James E Howard

Ray S Mckaig

A method includes: filling a chamber having a recirculating valve, a piston, a cap valve, an injector valve and an injection orifice with a liquid by closing the injector valve and circulating the liquid from a source through the recirculating valve and the cap valve; then isolating the chamber from the source by closing the recirculating valve and the cap valve then allowing pressure within the chamber to follow a cylinder pressure by mechanically coupling the cylinder pressure into the chamber; and energizing an injector coil with electric current that pulls a solenoid assembly in an upward direction opening the injector valve, further motion of the solenoid assembly drawing the piston upward, wherein liquid in the chamber is compressed by the piston to a higher pressure than the cylinder pressure, which has the effect of injecting an electronically controlled stream of liquid out of the chamber through the injection orifice.

Pressure compensated fuel injector with solenoid pumping

A method of operating a pressure compensated fuel injector includes: filling a fuel chamber with a charge of fuel by closing an injector valve and circulating a fuel from a fuel source through a plurality of recirculating valves and a cap valve; then isolating the fuel chamber and the charge of fuel from the fuel source; then equalizing a pressure within the fuel chamber to a rising pressure outside the fuel chamber by reducing a volume of the isolated fuel chamber; and then activating a solenoid that is coupled to the injector valve, opening the injector valve; and then further reducing the volume of the isolated fuel chamber to apply an over pressure within the chamber, pumping fuel from the fuel chamber through the injection orifice.

Pressure compensated fuel injector

Methods and apparatus are described for a reciprocating combustion engine. A method includes operating a dual-piston engine including introducing a gas into a pair of combustion chambers; introducing a fuel into the pair of combustion chambers; compressing the gas; combusting the gas and the fuel; and exhausting combusted gases. Each of the pistons drives a reciprocating crankshaft that protrudes through a cylinder wall and cooperatively rotate a pair of rotors by engaging substantially sinusoidal cam tracks on the rotors. An apparatus includes a cam driven, concentric drive rotary-valve dual-piston engine.

Reciprocating combustion engine

Pulse communications using precision timing includes detecting a pulse stream from a pulse code modulated carrier signal; transforming the pulse stream into a reshaped pulse stream; transforming the reshaped pulse stream into a counter gate stream; and recovering a data stream from the counter gate stream. The reshaped pulse stream is transformed into the counter gate stream with a digital circuit.

Precision timing pulse width communications transforming reshaped pulse stream

Methods are described for an optical fan-out and broadcast interconnect. A method includes operating an optical fan-out and broadcast interconnect including: fanning-out an optical signal from an optical signal emitter, of one of a plurality of nodes, with a diverging element of one of a plurality of optics; and broadcasting the optical signal to one of a plurality of receivers of all of the plurality of nodes with a light collecting and focusing element of all of the plurality of optics, wherein the plurality of optics are positioned to define an optics array, the plurality of receivers are positioned to define a receiver array that corresponds to the optics array and the plurality of nodes are positioned to define a node array that substantially corresponds to the receiver array and the optics array.

Optical fan-out and broadcast interconnect methodology

Systems and methods are described for pulse communications using precision timing. A method includes digitally pulse coding a data stream; and modulating a carrier signal using the digitally pulse coded data stream.

Precision timing pulse width communications

Methods and apparatus are described for integrated circuit optical signal emitters. A method includes emitting an optical signal from a gas plasma that is RF inductively coupled to an integrated circuit including a gas plasma discharge device having an inductive coil. Emitting includes magnetically energizing the inductive coil with the integrated circuit to induce a discharge from the gas plasma.

Integrated circuit optical signal emitters

Methods and apparatus are described for an optical fan-out and broadcast interconnect. A method includes operating an optical fan-out and broadcast interconnect including: fanning-out an optical signal from an optical signal emitter, of one of a plurality of nodes, with a diverging element of one of a plurality of optics; and broadcasting the optical signal to one of a plurality of receivers of all of the plurality of nodes with a light collecting and focusing element of all of the plurality of optics, wherein the plurality of optics are positioned to define an optics array, the plurality of receivers are positioned to define a receiver array that corresponds to the optics array and the plurality of nodes are positioned to define a node array that substantially corresponds to the receiver array and the optics array.

Optical fan-out and broadcast interconnect

Pulse width communications using precision timing

The invention constitutes a unique hardware zero overhead interrupt and task change mechanism for the reduction or elimination of interrupt latency and task change processing overhead delays in computer architectures. Without loss of time, the system performs complete task state saving and restoration between one cycle and the next without software intervention. For each Central Processing Unit () register, the invention uses one or more auxiliary latches () wherein one latch () is used as the 'running' latch and one of the auxiliary latches is attached to task storage memory. The invention swaps connections between alternate 'running' registers and auxiliary registers while transferring other tasks to and from task storage memory (). The invention provides a task linking system to allow the linking of tasks for the mandatory sequential execution of the linked tasks. Further, the invention includes a priority &#x201c;impatience&#x201d; counter system to increase the relative priorities of various tasks as they approach their task deadlines.

Zero overhead computer interrupts with task switching

A method for the orderly execution of multiple tasks in a data processing system and a circuit for implementing that method include a plurality of task modules which construct bids based upon the order of the task and its priority. The highest priority highest order number tasks are switched to available system execution resources. The system permits the orderly execution of round-robin task sets in an environment of dynamically changing priorities. When a round-robin task set is interrupted, the system is able to return to the round-robin task set after execution of the higher priority task at the exact point the interruption occurred.

Dynamic multilevel task management method and apparatus

A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse (). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter (). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.

Digital to analog convertor

An analog to digital convertor includes a pulse width modulated circuit (PWM) responsive to an analog parameter of an analog signal. The PWM circuit generates a pulse having a duty cycle proportional to the analog parameter. A counter generates a plurality of counterpulses during the pulse duty cycle and a sub-cycle pulse generator generates a series of subcycle pulses during each of the counterpulses. A latch circuit latches the state of the subcycle pulse generator at a predetermined time relative to the termination of the PWM pulse and a logic circuit counts the number of counterpulses which are generated during the PWM pulse. A most significant bit number is represented by the number of counter-pulses and a least significant bit number is determined by the state of the subcycle pulses in the latch. These two numbers added together provide a digital number representative of the analog parameter.

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Vancouver, WA, United States of America

Brian Donovan