Cirrus Logic Inc.

Maxim Integrated Products, Inc.

Brian David Trotter

John L Melanson

Bruce Eliot Duewer

Matthew Derrell Felder

Johann Guy Gaboriau

Jason Powell Rhode

Zhong You

Timothy Thomas Rueger

Aryesh Amar

Melvin L Hagge

Heling Yi

Thomas D Stein

A method for developing TDM data with embedded control data includes obtaining signal data and control data, formatting the signal data and the control data into a plurality of channels of a DIN signal, and transmitting the DIN signal on one line of a 3-bit TDM bus. A multichannel input device includes a control extractor receptive to the three-bit TDM bus and operative to extract CNTL data from the DIN data, a DAI receptive to the 3-bit TDM bus and the channel select input and operative to develop a SIGNAL data output, and a DAC block including a DAC, the DAC block being receptive to the SIGNAL data and the CNTL data.

Method and apparatus for controlling a multichannel TDM device

A multi-channel signal processing system reduces electromagnetic interference (EMI) by staggering pulse edges of one or more pulse-width modulated signals (PWM signals) to prevent pulse edge overlap with at least one of the other PWM signals and inverting at least one of the PWM signals. Staggering and inverting the PWM signals reduces the total EMI power at any given time generated by the multi-channel signal processing system. Pulse edges can be staggered by advancing or delaying a pulse edge for one or more channels. Pulses can be staggered and inverted using static interleave and inversion subsystems or dynamically using controllable interleave and inversion control systems. In at least one embodiment, the multi-channel signal processing system includes high power, half-bridge amplifiers for each channel. The timing and phases of the PWM signals can be determined to reduce EMI from the half-bridge amplifiers caused by the PWM signals.

Multi-channel pulse width modulated signal interleave and inversion

A constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus provides improved dynamic range in a noise-shaped CEM ternary pulse generator. A noise shaper shapes an input signal that is supplied to a pair of CEMs through a mismatch shaper or other code splitter that assigns unequal pulse width portions (the extra count in odd counts) between the pair of CEMs. The range of pulse width out of the CEMs can then be allowed to extend to the full sample period for one or possibly both of the CEMs in a given cycle. A control circuit overrides the mismatch shaper's assignment of the unequal pulse width portions when a previous pulse period yielded no transition from a given CEM, so that the given CEM is guaranteed to have a transition in the current pulse period.

Constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus

The signal processing system includes a pulse width modulator (PWM) that receives input signals from a delta sigma modulator. The PWM generates an output signal having successive frames of PWM patterns. Modifying loop filter data, such as a loop filter output signal, of the delta sigma modulator modifies a delta-sigma modulator quantizer output signal, which in turn changes the frame-to-frame duty cycles of the pulse width modulator output. PWM patterns corresponding to substantially similar delta sigma modulator input signal levels have substantially identical pulse widths. The signal processing system shifts rising and falling edges of pulse width modulator output signals relative to pulse width modulated signals generated from unmodified signals by a quanta of time greater than any deviation between the pulse widths. The signal processing system shifts pulse edges of PWM patterns to spread the spectrum of intra-channel and inter-channel harmonic frequencies.

Signal processing system with modified delta sigma modulator quantizer output signals to spread harmonic frequencies of pulse width modulator output signals

A method and apparatus for reducing noise in a digital-to-analog converter (DAC) having a chopper amplifier output stage provides improved DAC performance. A switched-current output provided from a digital filter is coupled to the input of a chopper amplifier. The current switches are non-uniform, so that extra zeros are provided at the chopping frequency of the chopping amplifier, thereby reducing noise that would otherwise be aliased in-band at the output of the chopper amplifier. The current switches may include a first set of half-magnitude switches followed by a set of full-magnitude switches and finally by another set of half-magnitude switches having a size equal to that of the first set.

Method and apparatus for reducing noise in a digital-to-analog converter (DAC) having a chopper output stage

A centered-pulse consecutive edge modulation (CEM) method and apparatus provides a pulse output that advantageously exploits the full edge update rate of the CEM while providing substantially centered pulses. The method and apparatus also operate without substantial delay in the input control path. The apparatus includes a delta-sigma noise shaping modulator followed by a CEM that receives an output of the delta-sigma modulator quantizer. A non-linear correction signal is applied with polarity alternating at each edge and is applied to the quantizer input or is designed into the quantizer transfer function. The non-linear correction signal compensates for the noise-shaping modulator output such that the expected rising edge and falling edge widths of the CEM output pulses are substantially equal with respect to a DC input to the delta-sigma modulator.

Centered-pulse consecutive edge modulation (CEM) method and apparatus

A method of performing digital to analog conversion includes generating a pulse width modulated data stream and another pulse width modulated data stream, encoding patterns of the pulse width modulated data stream selected to minimize distortion in the another pulse width modulated stream caused by edges in the pulse width modulated data stream. The pulse width modulated data stream and the another pulse width modulated data stream are converted into an analog signal and another analog signal converting in corresponding digital to analog conversion elements and the analog signal and the another analog signal are summed to generate an analog output signal.

Methods for output edge-balancing in pulse width modulation systems and data converters using the same

Methods and apparatus are provided for receiving DSD data in phase modulation mode using a single clock signal. Either the bit clock or phase signal may be used.

Single clock data communication in direct stream digital system

A method of operating a delta-sigma modulator by providing a variable-level quantizer, which selectively enables an additional quantizer level(s) during a ramp up sequence of the modulator. The additional quantizer level(s) is/are disabled during normal operation. The quantizer truncates a summer output and selectively enables the additional quantizer levels by clipping the truncated sum within a first range of quantizer levels during the ramp up sequence and within a second range of quantizer levels during normal operation in which there are more quantizer levels in the first range than in the second range. The quantizer preferably enables at least two additional quantizer levels at a low end of the quantizer range. For example, the range of quantizer levels for normal operation of the modulator can be from &#x2212;6 to +6, while the range of quantizer levels for ramp up operation of the modulator can be from &#x2212;8 to +7.

Multibit delta-sigma modulator with variable-level quantizer

A pulse width modulator includes at least one input for receiving an input signal and pulse width modulation circuitry for generating a pulse width modulated stream and another pulse width modulated stream. The pulse width modulated stream and the another pulse width modulated stream are nominally out of phase and together represent the received input signal. A summer sums the pulse width modulated stream and the another pulse width modulated stream to generate an analog output signal.

Data converters with ternary pulse width modulation output stages and methods and systems using the same

An apparatus and method for converting digital input signals sampled at different rates to analog signals includes a digital to analog converter for each digital input signal. Each digital to analog converter receives a digital input signal and a clock signal corresponding to the sampling rate of the received digital input signal. The apparatus can also receive a set of sample rate signals indicating the sampling rate for each digital input signal. The sample rate signals are used to route each digital input signal, along with a corresponding clock signal, to a corresponding digital to analog converter (DAC). A clock error signal controls routing of the digital input signals to the DACs as well as operation of the DACs. A clock divider and ratio detector module generates the clock error signal based on intermediate clock error signals that correspond to the sample rates.

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Austin, TX, United States of America

Brian David Trotter