International Business Machines Corporation

Brian David Allison

Joseph Allen Kirscht

Elizabeth A McGlone

Scott Douglas Clark

Brian Thomas Vanderpool

Patrick M Bland

Wayne Melvin Barrett

Ryuji Orita

Susumu Arai

John Monastero

A zipper locking hasp is described which adapts to most conventional zippers without modification to the zipper or to the movable slider parts of a zipper. The hasp is comprised of a plate component with prongs pivotally joined to a channel component. The plate component is fabricated having narrow prongs designed to fit through the conventional aperture present on most zipper sliders. In normal operation, when a zipper is closed, a pair of sliders is brought together along the zipper chain. When the hasp is open, the prongs formed by the plate are inserted through apertures in adjacent sliders which inhibits movement of each slider relative to one another. When the hasp is closed, holes provided in the plate and channel assembly are aligned. A shackle of a padlock can be inserted through the aligned holes keeping the plate and channel components mated locking the zipper.

Zipper locking device

A computer system, computer program product, and method implement dynamic physical memory reallocation. A system management interface (SMI) Handler and an Operating System (OS) are arranged for exchanging communications. Periodically the SMI Handler queries the operating system to identify a percentage of available memory currently being utilized. Responsive to the identified percentage of available memory currently being utilized, physical memory is dynamically reallocated.

Implementing dynamic physical memory reallocation

A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller includes a scrub controller configured to output more than one scrub request during a particular request selector cycle. The memory controller includes a request selector that services a read request, a write request, or one of the scrub requests during a request selector cycle.

Efficient scheduling of background scrub commands

A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of relatively light memory workload versus a period of relatively heavy workload. The memory controller provides a relatively higher priority for scrub requests near an end of a scrub period if scrub progress is behind an expected scrub progress.

Scheduling of background scrub commands to reduce high workload memory request latency

In a method of translating a physical memory address to a device address in a device memory space, a fast address translate of the physical memory address, adapted to translate addresses in uniformly configured device memory space, is performed thereby generating a first translated address. A full address translate of the physical memory address, adapted to translate addresses in non-uniformly configured device memory space, is also performed thereby generating a second translated address. Boundaries of a uniform portion of the device memory space are identified, to which the physical memory address is compared to determine if the physical memory address is in the uniform portion of the device memory space. When the physical memory address is in the uniform portion, the first translated address is selected as the device address. Otherwise, the second translated address is selected.

Memory controller and method for multi-path address translation in non-uniform memory configurations

A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

Memory controller granular read queue dynamic optimization of command selection

Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.

Directing interrupts to currently idle processors

A method and apparatus are provided for implementing input/output IO data management with an I/O buffer (IOB) directory in a compressed memory subsystem. Processor and I/O commands destined for a system memory are identified. I/O cacheline stores are accumulated in a free area of memory until a full block of data is received with only a directory to the data maintained on a memory controller chip. Then a pointer swap is provided to replace the existing compression block.

Method and apparatus for I/O data management with an I/O buffer in compressed memory subsystem

A method and apparatus are provided for implementing locking of non-data page operations in a memory system. In the method for implementing locking of non-data page operations of the invention, checking for a look aside buffer invalidate request is performed. Responsive to identifying a look aside buffer invalidate request, a real address is locked for the look aside buffer invalidate request. Then checking for a non-data page operation is performed. Responsive to identifying a non-data page operation, checking for the non-data page operation to complete is performed. Responsive to identifying the completed non-data page operation, the real address is unlocked for the look aside buffer invalidate request. Only a lock is placed on the page for a non-data page operation. A look aside buffer invalidate sequence is not performed for the non-data page operation.

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Rochester, MN, United States of America

Brian David Allison