Intel Corporation

Brian D Possley

David M Puffer

Kurt B Robinson

James Chapple

Ray Askew

Thomas E Dever, Ii

A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Memory controller hub interface

Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.

Gate array architecture

In accordance with one embodiment of the invention, a system includes an integrated circuit that has a compensation value generator. The compensation value generator processes multiple compensation values to generate a compensation value that may be used by compensation circuitry.

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Chandler, AZ, United States of America

Brian D Possley