Advanced Micro Devices Corporation

Globalfoundries Inc.

Brian D McMinn

James K Pickett

Mitchell K Alsup

Benjamin T Sander

Thomas W Lynch

Robert M Perlman

David B Witt

Stephen C Horne

Gerald David Zuraski, Jr

Teik-Chung Tan

Michael K Ciraula

W Kurt Lewchuk

Prem Sobel

Smeeta Gupta

Dale E Gulick

David S Christie

Rupaka Mahalingaiah

Stephan G Meier

Eric W Mahurin

Derrick R Meyer

Anthony M Petro

Paul C Miranda

Gregory William Smaus

Michael A Filippo

David Edward Kroesche

William McGee

Karthikeyan Muthusamy

Geoffrey S S Strongin

Gopi Ganapathy

Robert C Thaden

Thomas Burd

Glenn A Tamura

Michael E Bates

Arun Chandra

Richard L Bartolotti

Raju Vesgesna

Robert H Perlman

R Tod Calvin

Robert D Gowin, Jr

A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.

Constraint management and validation for template-based circuit design

A system and method for scheduling operations using speculative data operands. In one embodiment, a system may include a scheduler configured to store a speculative source tag and a non-speculative source tag for an operand of an operation and an execution core configured to execute operations issued by the scheduler and to output result tags identifying operands generated by executing the operations. The scheduler may be configured to determine whether the operation is ready to issue by comparing the speculative source tag, but not the non-speculative source tag, to the result tags output by the execution core unless an incorrect speculation has been detected. If an incorrect speculation has been detected, the scheduler may be configured to determine whether the operation is ready to issue by comparing the non-speculative source tag, but not the speculative source tag, to the result tags output by the execution core.

System and method for scheduling operations using speculative data operands

A data processor () includes an instruction cache () and a secondary cache (). The instruction cache () has a plurality of cache lines. Each of the plurality of cache lines stores a first plurality of bits () corresponding to at least one instruction and a second plurality of bits () associated with the execution of the at least one instruction. The secondary cache () is coupled to the instruction cache () and stores cache lines from the instruction cache () by storing the first plurality of bits () and a third plurality of bits () corresponding to the second plurality of bits (). The third plurality of bits () is fewer in number than the second plurality of bits ().

Data processor having a cache with efficient storage of predecode information, cache, and method

A microprocessor is configured to provide port arbitration in a register file. The microprocessor includes a plurality of functional units configured to collectively operate on a maximum number of operands in a given execution cycle, and a register file providing a number of read ports that is insufficient to provide the maximum number of operands to the plurality of functional units in the given execution cycle. The microprocessor also includes an arbitration logic coupled to allocate the read ports of the register file for use by selected functional units during the given execution cycle.

Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots

A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache for storage in one of the plurality of trace cache entries. The trace generator may be configured to detect an exceptional instruction within the group of instructions and to prevent the exceptional instruction from being stored in a same one of the plurality of trace cache entries as any non-exceptional instruction.

System and method for handling exceptional instructions in a trace cache based processor

A memory controller includes a power mode sensitive reordering device coupled to receive a power mode indication. The memory controller includes a selectable high and low power mode. An indication of which of the high and low power modes is selected is coupled to the power mode sensitive reordering device as the power mode indication. In the low power mode, memory transactions are reordered to minimize power consumption in memory devices controlled by the memory controller.

Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions

An apparatus comprises a buffer comprising a plurality of entries, a plurality of age vectors, and a control circuit coupled to the buffer. Each of the age vectors corresponds to one or more of the entries. Responsive to data being provided to the buffer to be written to at least a first entry, the control circuit is configured to generate a first age vector. The first age vector corresponds to the first entry, and is indicative of which of the plurality of entries contain data that is older than the data being written to the first entry. The control circuit is configured to select an entry for reading responsive to the plurality of age vectors. The selected entry has an attribute used to select the selected entry, and other entries indicated as storing older data in the age vector corresponding to the selected entry do not have the attribute.

Circular buffer using age vectors

A mapper circuit with backup capability. In one embodiment, the mapper circuit may store associations between physical register names (PRNs) and logical register names (LRNs) in a plurality of storage locations, each of the storage locations corresponding to a speculative state. One of the storage locations may store a LRN-to-PRN mappings for a current speculative state, while the other storage locations may store LRN-to-PRN mappings for previous speculative states. In a case where the processor is required to back up (e.g., such as in the case of a branch misprediction), one of the mappings associated with a previous speculative state may be reverted to an association with the current speculative state.

Mapper circuit with backup capability

A method and apparatus for retaining flag values when an associated data value dies. A first storage circuit includes a free list for storing physical register names (PRNs) and indications indicative of whether a physical register associated with a PRN was assigned to store a logical register result and flag results of a first instruction and a logical register result and a subsequent instruction which overwrites the logical register result but not the flags. A second storage circuit stores PRNs separate from the free list. The first and second storage circuits output first and second PRNs to a selection circuit. If the first indication (associated with the first PRN) is in a first state, the selection circuit may provide the first PRN to a mapper for assignment to a logical register. If the first indication is in a second state, the second PRN may be provided to the mapper.

Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming

Integrated circuits having multiple independently accessible microcode ROMs. An integrated circuit may include a microcode unit and a plurality of microcode ROMs fabricated within the same integrated circuit. The microcode unit may be configured to receive a microcoded instruction and to identify a microcode routine that corresponds to the microcoded instruction. The microcode ROMs may collectively store the microcode routines that implement the microcoded instructions of a complex instruction set, and different microcode ROMs may have different access times. At least one of the microcode ROMs may output operations included in the microcode routine in response to the microcode unit identifying the microcode routine. Microcode routines having more performance criticality may be stored in a microcode ROM having a smaller access latency than the access latency of a microcode ROM in which microcode routines having less performance criticality are stored.

Integrated circuit with multiple microcode ROMs

An apparatus comprises a buffer comprising a plurality of entries, an insert pointer, a delete pointer, a plurality of first control circuits coupled to the buffer, and a second control circuit coupled to the buffer. The entries are logically divided into a plurality of groups. Each of the first control circuits corresponds to a respective group and selects an entry from the respective group for potential reading from the buffer. Furthermore, each of the first control circuits, in the event that the delete pointer indicates a first entry in the respective group and the insert pointer wraps around the buffer and indicates a second entry in the respective group, selects the first entry if the first entry is eligible for selection. The second control circuit selects a first group, and the entry selected from the first group by the first control circuits is the entry read from the buffer.

Circular buffer using grouping for find first function

An efficient clock start and stop apparatus for clock forwarded system I/O. The apparatus may include a buffer coupled to receive incoming data from a data source. The buffer is clocked by a first clock signal that is provided by the data source. The buffer is configured to store the incoming data in a plurality of sequential lines in response to the first clock signal. The buffer may be further configured to store a plurality of bits in a plurality of occupied-bit registers. Each one of the plurality of occupied-bit registers indicates that data is present in a corresponding sequential line in the buffer. The apparatus may further include a clock gate circuit coupled to the buffer and configured to provide a second clock signal. The clock gate circuit may be further configured to start the second clock signal when valid data is present in the buffer and to stop the second clock signal when no data is present in the buffer.

Apparatus for stopping and starting a clock in a clock forwarded I/O system depending on the presence of valid data in a receive buffer

A system and method for transferring data using an early response signal to indicate subsequent transmission of data after a fixed latency, wherein the signal and data are transferred from a first clock domain to a second clock domain using a clock skipping technique. In one embodiment, an early response signal is transmitted by a first device k clock pulses prior to transmission of the data. The receiving device, which is operating at a higher clock rate, receives the early response signal and delays the signal by the number of skipped pulses which will occur in the second clock domain before the occurrence of the k valid pulse. The second device employs a skip pattern generator to generate a signal indicative of this number of skipped pulses and provides the number to a delay circuit which delays the early response signal for an this number of clock pulses. The delayed early response signal is then output to the appropriate logic to indicate the latency of the subsequent data transfer.

Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios

A method and related system for transferring data between systems having different clock domains. A skip signal generation circuit calculates substantially simultaneously with the transfer of data which signals of the faster clock domain should be skipped to ensure proper operation. The skip signal generation circuit makes this determination using values representing the faster and slower frequencies of each clock domain. These values are obtained either from preset values integrated in some form onto the microprocessor substrate, or may be written to the microprocessor by external circuitry and software. The skip signal generation circuit is capable of calculating skip patterns for any ratio of faster to slower frequency and is not constrained to have integer or half-integer ratios of the faster and slower clock domains.

Method for transfering data between two different clock domains by calculating which pulses of the faster clock domain should be skipped substantially simultaneously with the transfer

A storage circuit for an integrated circuit is configured to couple to a first power supply voltage (e.g. a V power supply voltage used by other circuitry within the integrated circuit) in response to a deassertion of a hold signal and configured to couple to a second power supply in response to an assertion of the hold signal. The second power supply voltage may be the hold signal voltage or another power supply voltage separate from the V power supply voltage. The hold signal may be asserted and the V power supply voltage may be removed. Leakage current in circuits powered only by the V power supply voltage may be eliminated, while the storage circuit may retain its stored value. A system including the integrated circuit and a method for managing power in the system.

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Buda, TX, United States of America

Brian D McMinn