Emc Corporation

Brian D Magnuson

Daniel Castel

Brian K Campbell

Ofer Porat

John K Walton

Kendell Alan Chilton

Christopher S MacLellan

Stephen Lawrence Scaringella

Gregory S Robidoux

Mark Botelho

A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.

Memory system having daisy chained memory controllers

A system having a plurality of printed circuit broads each one having an electrical component thereon. A backplane carries a signal indicative of a performance characteristic of the electrical components on the plurality of printed circuit boards plugged into such backplane. The performance characteristic may be, for example component speed, operating protocol, etc. System start-up is interrupted upon detection of such incompatibility. After start up, upon plugging an additional printed circuit broad having an electrical component thereon with an operating incompatible with the electrical components on the plurality of printed circuit boards into the backplane, the electrical component on such additional printed circuit will not be electrically coupled to the electrical component on the additional printed circuit board from the electrical components of the plurality of printed circuit boards.

System having backplane performance capability selection logic

A system interface having a backplane adapted to have plugged therein director boards and memory boards. Each one of such director boards includes director board transmit/receive units. Each one of the director board transmit/receive units is associated with a corresponding one of the of memory boards. Each one of the director board transmit/receive units is adapted to be disabled in the absence of the one of the memory boards associated with such one of the director board transmit/receive units. Each one of the memory boards includes memory board transmit/receive units. Each one of the memory board transmit/receive units is associated with a corresponding one of the director boards. Each one of the memory board transmit/receive units is adapted to be disabled to prevent transmit/receive data therethrough in the absence of the one of such director boards associated with such one of the memory board transmit/receive units.

Data storage system having port disable mechanism

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Somerville, MA, United States of America

Brian D Magnuson