Altera Corporation

Other

Altera Corporation San Jose Ca

Brian D Johnson

Andy Louie Lee

Cameron R McClintock

Richard G Cliff

Paul Leventis

David Lewis

Srinivas T Reddy

Vaughn Betz

Christopher F Lane

Chiakang Sung

Joseph Huang

Yan Chong

Philip Pan

John E Turner

Wanli Chang

Chiao Kai Hwang

Chris Lane

Ketan H Zaveri

Giles V Powell

Richard Yen-Hsiang Chang

David Edward Jefferson

Chris Wysocki

Triet M Nguyen

Michael Chan

Mario E Guzman

Alexander Marquardt

Keith Duwel

David Cashman

Hyun Mo Yi

Vikram Santurkar

Richard Y Chang

Stephanie T Tran

Toan Thanh Nguyen

Quyen Doan

Nobuyuki Fujiwara

Vaughn Timothy Betz

Cameron Mcclintock

The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

Multiple data rate memory interface architecture

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

PLD architecture for flexible placement of IP function blocks

A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

High performance memory interface circuit architecture

High-performance memory interface circuit architecture

Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Von the range of signals passed by single-transistor passgates is reduced. In one arrangement, the V-Vlimit for signals propagated through NMOS passgates is raised by applying a higher V; in another arrangement, the Vis lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Passgate structures for use in low-voltage applications

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Sunnyvale, CA, United States of America

Brian D Johnson