Apple Inc.

Brian D Howard

Robert L Bailey

Michael F Culbert

Keith Alan Cox

Josh P De Cesare

Richard Charles Williams

Dave Robbins Falkenburg

Daisie Iris Huang

Dave Radcliffe

David Radcliffe

Lesley B Wynne

William C Athas

Ian C Hendry

Dennis Joseph Boyle

David Gerard Conroy

Matt Herron

David Ferguson

James J Halicho

Mary B Johnson

David Blakely

Michael D Johnson

Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).

Methods and apparatuses for controlling the temperature of a data processing system

Methods and apparatuses for operating a data processing system

One embodiment of the present invention provides a system that switches from a first graphics processor to a second graphics processor to drive a display. During operation, the system receives a request to switch a signal source which drives the display from the first graphics processor to the second graphics processor. In response to the request, the system first configures the second graphics processor so that the second graphics processor is ready to drive the display. Next, the system switches the signal source that drives the display from the first graphics processor to the second graphics processor, thereby causing the second graphics processor to drive the display.

Method and apparatus for switching between graphics sources

A method and apparatus for viewing and/or analyzing the operations and logical states of an integrated circuit. The logical state of various flip-flops within the ASIC may be determined at a specified time. The embodiment may store these flip-flop states in a computer-readable data structure, such as a file or database. By repeating this process and incrementing or decrementing the time with each repetition, a more complete picture of the ASIC's operation may be captured. Additionally, the embodiment may graphically display the flip-flop states, for example as a graph or waveform.

Analyzing integrated circuit operations

A computer system includes a processor, a memory, first and second graphical processors that have different operating characteristics, a switching mechanism coupled to the graphical processors, and a display coupled to the switching mechanism. The switching mechanism is configured to couple a given graphical processor to the display, and is initially configured to couple the first graphical processor to the display. Furthermore, a program module, which is stored in the memory and configured to be executed by the processor, is configured to change a configuration of the switching mechanism thereby decoupling the first graphical processor from the display and coupling the second graphical processor to the display. Note that the changing of the configuration and switching module operations are configured to occur while an operating system is running and are based on the operating condition of the computer system.

Multiplexed graphics architecture for graphics power management

One embodiment of the present invention provides a system that includes an I/O descriptor cache that is accessed by a bus mastering I/O controller. The I/O descriptor cache stores descriptors that describe data to be transferred during corresponding I/O operations. The system also includes an I/O controller configured to control one or more I/O devices. This I/O controller is configured to access I/O descriptors stored in the I/O descriptor cache without having to access the main memory, thereby conserving I/O bandwidth and power.

I/O descriptor cache for bus mastering I/O controllers

Method and apparatus for analyzing integrated circuit operations

Devices are assigned to different buses at development time as well as dynamically during operation, based on actual performance. At development time, bus assignment can be determined based on experiments and direct observation of how devices behave in various configurations. At run time, load on each bus is preferably measured periodically, and when it is uneven, devices are reallocated to different buses. In an alternative embodiment, a user can specify a preference for using more or fewer buses in order to optimize operation for efficiency or lower power consumption.

Dynamically allocating devices to buses

A controller (or controller chip) providing reduced power consumption without impacting performance is disclosed. The controller monitors activity of components within the controller which require access to a local memory, and then decreases a clocking frequency for a memory interface to the local memory when the monitoring indicates that reduced amounts of activity are present. Following such a decrease in the clocking frequency, when increased amounts of activity are detected, the clocking frequency is increased for high performance operation. The controller thus tailors the clocking frequency for the memory interface in accordance with the amount of activity of these components that require access to the local memory so that overall less power is used by the controller yet the performance is essentially not hindered. In one embodiment, the controller is a graphics controller, as such controllers require access to local memories.

Power managed graphics controller

A method and an apparatus for rotating images on a computer system is disclosed. The system includes a processor for accessing an image frame buffer using a set of CPU addresses, a memory for storing the frame buffer, a controller for directing the pixel data of the frame buffer to a display device using a set of controller addresses. The two sets of addresses are not necessarily the same. In fact, numerous advantages could be had from manipulating those two sets of addresses resulting in image rotation operations for the display device.

Method and apparatus for display image rotation

Power management approaches for computer systems having one or more processors are disclosed. One power management approach provides hierarchical power management. The hierarchical nature of the power management provided by the invention has various levels of power management such that power consumption of the computer system is dependent upon the amount of work placed on the processing resources of the computer system. Another power management approach pertains to deterministic handshaking provided between a power manager and one or more controller units. The deterministic handshaking provides for more reliable and controllable transitions between power management states which have associated power management taking place in the controller units. The power management approaches are suitable for use with a single-processor computer system or a multi-processor computer system.

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Menlo Park, CA, United States of America

Brian D Howard