Pmc-Sierra, Inc.

Brian D Gerson

Charles Kevin Huscroft

Kris Iniewski

Vernon Robert Little

Colin Harris

Graham B Smith

David LeBlanc

Kenneth William Ferguson

Stephen Julien Dabecki

John Richard Bradshaw

Curtis Brian Lapadat

Andre Ivanov

Martin Mallinson

Kevin Huscroft

Barry Benjamin Hagglund

Kamal Dalmia

David Leblanc

Test device (DUT) current flow is mirrored through a capacitor. If the mirrored current is switched to bypass the capacitor, the capacitor discharges. Otherwise, the mirrored current charges the capacitor. The charging capacitor's voltage rise time is proportional to the DUT's IDDQ current. Several IDDQ reference values can be derived, each representing quiescent state operation of a defect-free copy of the DUT. An IDDQ test value is derived for each IDDQ reference value. Each test value represents quiescent state operation of the DUT after application of the test vector which produced the corresponding reference value. The reference values are compared to their corresponding test values and a plurality of scaling factors derived. Each scaling factor represents a proportionality between corresponding reference and test values. The DUT is &ldquo;non-defective&rdquo; if the scaling factors are equal within a predefined error range . Otherwise, the DUT is &ldquo;defective&rdquo;.

High-speed, adaptive IDDQ measurement

A user network interface device for interfacing between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) which is characterized by a continuous stream of frames of data and an asynchronous transfer mode (ATM) characterized by a non-continuous stream of cells of data. The user network interface device includes an integral phase lock loop circuit to recover clock and data from an encoded incoming stream of data. In another embodiment, the network interface device synthesizes a high speed transmit clock from a low frequency reference source.

Integrated user network interface device for interfacing between a sonet network and an ATM network

A resistor having a diffused impurity region in a semiconductor substrate, an insulated gate surrounding and defining the resistor, and a pair of separated conductive contacts to the diffused region within the boundary of the insulated gate for applying and receiving current passing through the resistor.

Polysilicon defined diffused resistor

According to the invention there is provided a method of signal coding that permits high speed data transmission over multiple pairs of UTP-5 cable from a transmission end to a receiving end which includes, at the transmission end, separating an incoming frame of data into a plurality of byte streams with a predefined sequence of bytes assigned to each of the streams, encoding every 2 bits of data in each stream into one of 4 logical voltage levels forming a symbol or quat thereby reducing the symbol or baud rate by 50% and inserting an escape sequence into one or more of the streams consisting of a sequence of zero's followed by a control code to indicate a transition from one state to another. At a receiving end, the method further includes reading the escape sequence and decoding the signals in accordance with the code contained in the escape sequence.

Line coding technique for efficient transmission and delineation of

A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.

CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL

A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for applying a stream of data generated by the data generating apparatus that has been jittered by the jittered clock to an input of the CRU, and apparatus for detecting a bit error rate of a data signal output from the CRU.

Built-in test scheme for a jitter tolerance test of a clock and data

An electrostatic discharge (ESD) protection structure for protection of a circuit to which an operation voltage is to be applied, comprising a silicon controlled rectifier (SCR) connected between ground and a pad of the circuit to be protected, the SCR including a resistor apparatus connected to the pad for controlling the breakdown voltage of the SCR, and apparatus for controlling the resistor apparatus to a high resistance value in the absence of the application of the operation voltage whereby the SCR is controlled to break down at a low ESD voltage which is lower than a circuit damaging voltage, and to be of low resistance value upon the application of the operation voltage whereby the SCR is controlled to break down at an ESD voltage which is higher than the low ESD voltage.

Low voltage silicon controlled rectifier structure for ESD input pad

A complementary metal oxide silicon (CMOS) data to emitter coupled logic (ECL) data translator system comprised of translator apparatus for receiving data signals from a CMOS circuit powered from a CMOS voltage power source, apparatus for powering an ECL circuit from the power source, a transmission line carrying output signals from the translator apparatus to the ECL circuit, having a predetermined characteristic, a load having the characteristic impedance connecting the transmission line to the power source, and the translator apparatus comprising apparatus for outputting a data signal on the transmission line which corresponds to the received data signals but having an amplitude compatible with the ECL circuit and referenced to a voltage of the power source.

High-speed CMOS pseudo-ECL output driver

A method of generating output clock pulses using a phase locked loop which includes a voltage controlled oscillator (VCO) is comprised of providing a sequence of data pulses and a sequence of reference clock pulses, resetting the phase locked loop to force the VCO to its lowest operating frequency, releasing reset of the phase locked loop and forcing the VCO to lock to a multiple of the frequency of the reference clock pulses, detecting the presence of data pulse transitions, in the event of detection of data pulse transitions, forcing the VCO to lock to the data pulses, and outputting output clock pulses from the phase locked loop.

Growing community of inventors

Coquitlam, Canada

Brian D Gerson