Xilinx, Inc.

Other

Brian D Erickson

Charles R Erickson

Bernardo A Elayda, Iii

Neil G Jacobson

Jesse H Jenkins, Iv

Sanjay Srivastava

Bin Dai

Sungnien Jerry Mao

Emigdio M Flores, Jr

Rosa M Y Chow

Pushpasheel Tawade

Patrick T Bever

Barry Wong

Bernardo Elayda

David E Schweigler

Mark M Ng

Through-silicon vias (TSVs) are tested using a modified integrated circuit test probe array, an electron beam generation device, a beam direction control device and an electron beam detection device. The TSV extends through a silicon substrate with end portions exposed or accessible by contacts disposed on opposing upper and lower surfaces of the substrate. The test probe array includes a test probe that accesses the lower TSV end portion and applies an AC test signal. An electron beam is directed by the beam direction control device onto the upper substrate surface such that a beam portion reflected from the upper TSV end portion is captured by the electron beam detection device. Reflected beam data is then analyzed to verify the TSV is properly formed. Various scan patterns, different test signal frequencies and an optional resistive coating are used to enhance the TSV testing process.

Method for testing through-silicon vias at wafer sort using electron beam deflection

A wireless programmable logic device contains a wireless component and a programmable logic component. A remote wireless host can be used to program the programmable logic device. Some product designs require multiple programmable logic devices. When wireless programmable logic devices are used in the design, all of them can receive data and commands from the host. As a result, the wireless host can control the order of configuration and the start time of these logic devices. There is no need to build glue logic for this purpose. Consequently, the efficiency in product design is improved. If there are problems in programming a programmable logic device, the host can log the failed operation in its memory. This information could be used to improve production flow.

Wireless programmable logic devices

Method and system for a programmable device programmer. The disclosure describes various embodiments for programming a target programmable device by a programmer. In one embodiment, the programmer determines availability of updated configuration data for a hardware component of the programmer. The programmer includes the software component coupled to the hardware component. An update mode of the hardware component is enabled in response to availability of the updated configuration data, and programming of the target programmable device is disabled while the hardware component is in the update mode. A programmable device internal to the hardware component is programmed with the updated configuration data while the hardware component is in the update mode, and the update mode is disabled in response to completion of programming of the at least one programmable device. A target programmable device may then be programmed by the programmer having the updated configuration data.

Transmitting configuration data to a target programmable device after updating an intermediate programmable device

A power control output circuit for a PLD that allows the PLD to selectively operate in either a low current (&ldquo;normal&rdquo;) output mode, or a high current power control mode. In one embodiment, the power control output circuit is incorporated into a special Input/Output Blocks (PC-IOB) of the PLD. When no power control function is needed, a high current output portion of the power control output circuit is deactivated by storing an associated data value a power control configuration memory cell of the PLD, and an output driver of the PC-IOB generates low current output signals on a device I/O terminal. To perform power control functions, a portion of the PLD's programmable logic circuitry is configured to generate a power control data signal, and the high current output portion of the power control output circuit is enabled by storing a corresponding data value in the power control configuration memory cell. When the power control data signal is generated while in the high current power control mode, the high current output circuit turns on a high current transistor that generates a high current power control output signal at the device I/O terminal.

System power control output circuit for programmable logic devices

A programmable logic device (PLD) including a non-volatile memory array for persistently storing configuration data, and a volatile memory array for temporarily storing the configuration data and controlling the various logic resources of the PLD to perform a user's logic operation. When the PLD is reset, an addressing circuit causes a column of non-volatile memory cells to transmit configuration data values to a corresponding column of volatile memory cells on a series of write lines. To verify that a configuration data value is successfully written from each non-volatile memory cell to a corresponding volatile memory cell, the data value transmitted on each write line is compared with the stored data value transmitted from each volatile memory cell on a corresponding read line. A control signal is generated when all of the data values transmitted on the write lines are equal to stored data values transmitted on corresponding read lines, thereby indicating that the configuration data values are successfully transferred to the column of volatile memory cells. The control signal is used to increment the address circuit, thereby addressing a next sequential column of non-volatile memory cells and associated volatile memory cells. Normal PLD operation is initiated when all configuration data is transferred.

Method and circuit for verifying configuration of programmable logic device

Apparatus and method for programming a programmable logic device (PLD) using a status bit to indicate whether in-system programming (ISP) has been completed. Complex electronic systems often use PLDs to interface to other elements of the system and to the outside environment. Such PLDs are reprogrammed by the system controller using the boundary-scan/JTAG access port, but a power failure may cause an unwanted termination of the programming cycle before all of the PLD internal logic, connections, and functional I/O pins are properly programmed. In such a situation, some or all of the PLD functional (input/output) pins could be driven to erroneous states such that other devices connected to them would be damaged or prevented from operating correctly. The status indicator is set to hold all PLD functional pins in a high impedance condition (tri-state) until programming or another non-mission mode of PLD operation is successfully concluded. Additionally, selected driver elements within the PLD can be disabled in the same way. In the event of an unexpected loss of power, the status indicator causes all PLD functional pins to come up in tri-state on restoration of power and therefore be unable to assert control of any other connected devices or busses. Likewise, selected drivers can also be disabled to prevent similar contention problems.

Method and apparatus for in-system programming with a status bit

A method and structure for testing static signal levels on an integrated circuit device using an electron beam deflection device. Each static signal is applied to a first terminal of a switch, such as an AND gate, an OR gate, or a pass transistor. An alternating control signal of approximately 1 MHz is transmitted to a second terminal of the switch such that the switch generates an output signal that is either constant (if the static signal is at a first level), or has a frequency equal to that of the alternating control signal (if the static signal is at a second level). The output signal is transmitted to a pad located on an exposed surface of the integrated circuit, where an electron beam deflection device is utilized to determine the static signal level by detecting the presence or absence of an alternating signal. A method for determining the voltage level of a signal includes applying the signal to the gate of a transistor and an alternating control signal to an input terminal. An electron beam deflection device is then utilized to measure the voltage level of a signal generated at an output terminal of the transistor. The voltage level of the signal is then calculated by adding the measured voltage level and a threshold voltage of the transistor.

Method and structure for viewing static signal levels on integrated

An integrated circuit combination includes a second piggy-back small integrated circuit chip mounted on the carrier of a first integrated circuit chip. The combination can be mounted on a board without requiring board space for interconnecting the first and second chips. The lid of the first chip is cut away so that the second chip can be mounted to the first without increasing the height of the combination over the height of the first chip. The two chips preferably comprise an FPGA and a PROM for programming the FPGA. The combination increases security as well as reducing board space because it is difficult to read a bitstream being transmitted from the PROM to the FPGA when the PROM is directly mounted on the FPGA.

Integrated circuit packaged for receiving another integrated circuit

A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal when neither of the high and low input signals is received. The inventive circuit drives three internally forwarded output signals from a single external signal source. Since this circuit may be duplicated for every pin on a device for which two cycle delays do not affect performance, availability of a third input state on N inputs allows 3.sup.N input codes as opposed to 2.sup.N for the conventional 'high' and 'low' levels normally available.

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Soquel, CA, United States of America

Brian D Erickson