Control Data Corporation

Brian D Borchers

Daniel J Baxter

Don A Daane

Judy L Teske

David H Allen

Michael F Maas

William G Ehrich

This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.

Flexible VLSI on-chip maintenance and test system with unit I/O cell

This application teaches that more accurate measurements of clock skew can be had by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip.

Clock monitor for use with VLSI chips

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Burnsville, MN, United States of America

Brian D Borchers