Monolithic 3d Inc.

Or-ment LLC

Destination 2d Inc.

Other

William Marsh Rice University

Monlithic 3d Inc.

Monolthic 3d Inc.

Monolitic 3d Inc.

Or-ment L.l.c

Brian Cronquist

Zvi Or-Bach

Deepak Chandra Sekar

Jin-Woo Han

Israel Beinglass

Jan Lodewijk De Jong

Zeev Wurman

Paul G Lim

Eli Lusky

Ze'ev Wurman

Kaustav Banerjee

Isreal Beinglass

Ravi Iyengar

J L De Jong

James Mitchell Tour

Albert Karl Henning

Jun Yao

Klaus Schuegraf

A conducting thin film structure or pattern which facilitates the insertion of dopant atoms, ions, or molecules into layered 2D materials including: a layered 2D material, an electrically isolative material disposed below the layered 2D material, where the layered 2D material has at least one layer, where the layered 2D material includes slots, where the slots include etched regions where the layered 2D material is at least partially etched away, where the etched regions include a width greater than 0.5 nm and less than 1 meter, where the layered 2D material is intercalation doped with at least one dopant, where the at least one dopant includes at least one intercalation doping agent, where the layered 2D material with the slots is fully intercalation doped (stage-1 intercalation) or partially intercalation doped, where a first portion of the layered 2D material is doped p-type, and a second portion is doped n-type.

Techniques, methods, and structures for rapid and efficient intercalation-doping of large-area multi-layered graphene sheets for transparent conductor applications, including solar cells and displays

A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.

3D semiconductor devices and structures with electronic circuit units

A diffusion-couple synthesis method using a graphene synthesis tool (GST) including: providing a substrate-load (SL) which includes first-prepared substrate (fPS) and second-prepared-substrate (sPS), where fPS includes a first-carbon-source (fCS), a first-sacrificial-diffusion layer (fSDL), and a first-device-level (fDL), where a first-dielectric-layer (fDiLy) is disposed atop fDL, where fSDL is disposed directly atop fDiLy, where fCS is disposed directly atop the fSDL, and where the sPS includes a secondCS, a secondSDL, and a secondDL, where secondDL is disposed atop the secondDL, where the secondSDL is disposed atop secondDiLy, where secondCS is disposed atop secondSDL; providing a GST capable of applying pressure and temperature to SL within a process chamber (PC); placing SL within PC; applying the pressure and the temperature to SL, where sPS is inverted and disposed above fPS, where fCS is in direct contact with secondCS; forming graphene at a first interface between the fDiLy and the fSDL and at a second interface between secondDiLy and secondSDL.

Throughput improvements for low-temperature/beol-compatible highly scalable graphene synthesis methods including processing in retasked tools

A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors, at least one metal layer, and third memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors, another at least one metal layer, and is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes; and a via connection through the second level and the third level, and where the fourth level includes at least one SRAM memory array.

3D memory devices and structures with memory arrays and metal layers

A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.

3D semiconductor device and structure with metal layers

An electrical passenger car, the electrical passenger car including: a battery pack; motor control electronics; a communication control unit; at least one electrically driven motor; wheels, where the wheels are connected to the at least one electrically driven motor; and sensors, where the sensors are connected to at least the motor control electronics, where the wheels include a first wheel and a second wheel, where the second wheel has a radius at least 7% greater than a radius of the first wheel, where the battery pack is mounted in the electrical passenger car frame such that the battery pack can be moved upward or downward, and where the electrical passenger car is designed to be driven mainly on a paved road.

Efficient electrical passenger car with motor control

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.

Multilevel semiconductor device and structure with image sensors and wafer bonding

A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.

3D semiconductor devices and structures with metal layers

A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.

A 3D semiconductor device including dicing including an etch process; and including: a first level including a single crystal layer, and a memory control circuit which includes first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

3D semiconductor device, structure and methods with memory arrays and connectivity structures

A transparent or semi-transparent conducting thin film structure or pattern which facilitates the insertion of dopant atoms, ions, or molecules into layered 2D materials, the film structure including: a planar sheet of layered 2D material, the layered 2D material having at least one layer disposed in a respective plane, an electrically isolative material, where the electrically isolative material is disposed below the layered 2D material, where the layered 2D material has at least one layer, where the layered 2D material is divided into islands of the 2D material, where separation of the islands of 2D material with respect to each other is greater than 0.5 nm and less than 1 meter, and where the islands of 2D material are intercalation doped with at least one dopant, and where the at least one dopant includes intercalation doping agents.

A diffusion-couple synthesis method using a graphene synthesis tool (GST) including: providing a substrate-load (SL) which includes first-preparedsubstrate (fPS) and second-prepared-substrate (sPS), where fPS includes a first-carbon-source (fCS), a first-sacrificial-diffusion layer (fSDL), and a first-device-level (fDL), where a first-dielectric-layer (fDiLy) is disposed atop fDL, where fSDL is disposed directly atop fDiLy, where fCS is disposed directly atop the fSDL, and where the sPS includes a secondCS, a secondSDL, and a secondDL, where secondDL is disposed atop the secondDL, where the secondSDL is disposed atop secondDiLy, where secondCS is disposed atop secondSDL; providing a GST capable of applying pressure and temperature to SL within a process chamber (PC); placing SL within PC; applying the pressure and the temperature to SL, where sPS is inverted and disposed above fPS, where fCS is in direct contact with secondCS; forming graphene at a first interface between the fDiLy and the fSDL and at a second interface between secondDiLy and secondSDL.

A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the second level includes second ESD circuits.

3D semiconductor device and structure including power distribution grids

A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.

3D semiconductor device and structure with connection paths

A 3D semiconductor memory, the memory including: a first level including first memory cells, first transistors, and a first control line, where the first memory cells each include one of the first transistors; a second level including second memory cells, second transistors, and a second control line, where the second memory cells each include one of the second transistors, where the second level overlays the first level, where the second control line and the first control line have been processed following the same lithography step and accordingly are self-aligned, where the first control line is directly connected to each source or drain of at least five of the first transistors, and where the second control line is directly connected to each source or drain of at least five of the second transistors; and an oxide layer disposed between the first control line and the second control line.

Growing community of inventors

San Jose, CA, United States of America

Brian Cronquist