Sandisk Technologies Inc.

Sandisk Corporation

Brian Cheung

Darmin Jin

William Chau

Paul A Lassa

Emmanuel De Muizon

Paul Paternoster

Steve Skala

Stan Chapski

A system for communicating high voltages for a semiconductor device is provided. One system includes a controller having an input pad and an output pad, each of the input pad and the output pad being coupled to a respective high voltage switch of the controller. The system also includes a plurality of semiconductor chips, where each of the plurality of semiconductor chips has at least one input pad coupled to a high voltage switch of a respective semiconductor chip. A high voltage that is higher than normal operation voltages of the semiconductor device is coupled from the input pad of the controller to the output pad of the controller via the coupled high voltage switches of the controller. The high voltage is further coupled from the output pad of the controller to the at least one input pad of the respective semiconductor chip via the high voltage switch coupled to the at least one input pad of the respective semiconductor chip. Methods for operating and providing high voltage inputs to one or more semiconductor devices are also provided.

Systems and methods for operating high voltage switches

Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

Apparatus and method for high voltage switches

A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.

Connection between an I/O region and the core region of an integrated circuit

Integrated circuits where the standard isolation cell, at power island boundaries, also includes a protection device, which clamps transient voltages.

Systems, circuits, chips and methods with protection at power island boundaries

Methods and systems for optimal decoupling capacitance in a dual-voltage power-island architecture. In low-voltage areas of the chip, accumulation capacitors of two different types are used for decoupling, depending on whether the capacitor is located in an area which is always-on or an area which is conditionally powered.

Integrated circuits and methods with two types of decoupling capacitors

Timing measurement is performed by a digital oscillator, using a calibration value which is calculated after chip fabrication is completed, and automatically loaded into selection logic at powerup.

Systems, modules, chips, circuits and methods with delay trim value updates on power-up

A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a 'de-glitching' time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.

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San Bruno, CA, United States of America

Brian Cheung