International Business Machines Corporation

Brian C Wilson

Anthony DeGroff Drumm

Robert Lowell Kanzelman

Lakshmi Narasimha Reddy

Louise Helen Trevillyan

Jagannathan Narasimhan

Scott Henry Mack

Zhuo Li

Charles Jay Alpert

Chin Ngai Sze

Gi-Joon Nam

Kent A Smith

Natarajan Viswanathan

Mark S Fredrickson

David Anthony Papa

Galen B Rhodes

Michael D Amundson

Victor A Acuña

Marcus Matthew Poplawski

Jeff S Geist

Gary E Moss

A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

Task-based multi-process design synthesis

The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

Accuracy pin-slew mode for gate delay calculation

In a first aspect, a first method of designing a circuit is provided. The first method includes the steps of (1) providing a model of an original circuit design including a latch; (2) providing a model of a modified version of the original circuit design, wherein the modified version of the original circuit design includes a set of latches associated with the latch of the original circuit design and voting logic having inputs coupled to respective outputs of latches in the latch set; and (3) during Boolean equivalency checking (BEC), injecting an error on at most a largest minority of the inputs of the voting logic to test the voting logic function.

Methods and apparatus for boolean equivalency checking in the presence of voting logic

Methods, apparatus and articles of manufacture are disclosed for a design automation application to evaluate a design automation task using an on-demand computer network. A requesting entity transmits the design automation task, along with a set of data used for testing, to a drop server box provided by the on-demand computer network. The design automation application is configured to process the design automation task and to prevent it from interfering with, or eavesdropping on, other tasks being executed in the on-demand environment and from interfering with the operation of the on-demand environment itself. The design automation application consumes available grid resources to complete the processing task.

e-Business on-demand for design automation tools

Methods and apparatus for Boolean equivalency checking in the presence of voting logic

Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays and/or wire length) may be realized at greatly reduced computational times when compared to conventional techniques that attempt to optimize each buffer tree.

Targeted optimization of buffer-tree logic

The present invention provides a method and a computer-readable program for providing generation of graphical congestion images during placement driven synthesis optimization. These graphical congestion images enable a design engineer to make changes and/or improvements to subsequent processes in the design flow before the current placement driven synthesis step completes, thus saving time. This information also provides valuable debug information to PDS developers.

Generation of graphical congestion data during placement driven synthesis optimization

An apparatus, program product and method utilize an interactive request server program to interface a plurality of client computers with a timing analysis program. The interactive request server program receives client requests from the plurality of client computers over a network, and, in response to each client request, accesses the timing analysis program to retrieve timing data based upon such client request and thereafter forwards the timing data to the client computer making such request. The interactive request server program may optionally be implemented using a web server program and an application server program, with the web server program interfacing with the client computers via an Internet-type interface, and the application server program interfacing with the timing analysis program using a programmatic interface supported by the timing analysis program. The web server, program and the application server program interface with one another through the use of scripts, which are executed by the web server in response to client requests, and which generate one or more commands that are issued to the application server program to control the timing analysis program via the programmatic interface.

Interactive client-server environment for performing collaborative timing analysis of circuit designs

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Rochester, MN, United States of America

Brian C Wilson