International Business Machines Corporation

Brian C Noble

Eric B Hultmark

David A Grosch

Marc Douglas Knox

Jody John Van Horn

Erik A Nelson

Gregory V Miller

Joel Thomas

Ann L Swift

A method, apparatus and computer program product for testing semiconductor products that combines multiple techniques. Depending on the requirements, different ones of the techniques are emphasized over the other techniques. The testing applies a technique to achieve a higher single defect acceleration parameter at the expense of a second parameter, thus enabling acceleration of defects that require higher voltage or higher temperature than a traditional 'Burn In' can achieve, which defects would otherwise go unaccelerated. The method manages the adaptation of the different techniques, e.g., how it decides to favor one technique over the other, and how it carries out the favoring of one or more particular techniques in a given test situation. Thus, acceleration to defectivity (defect type and quantity) may be tailored in real time by uniquely leveraging the duration spent in a given section of a process flow based on the prevalence of unique defect types.

Diversified exerciser and accelerator

Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.

Methods and apparatus for margin testing integrated circuits using asynchronously timed varied supply voltage and test patterns

An electronic device is provided comprising a stacked integrated circuit chip assembly wherein the top chip of the assembly is solder connected to the surface of an interconnection substrate with the other chips of the assembly being enclosed in a cavity in the interconnection substrate wherein the cavity and electrical connections of the assembly and between the substrate and top chip are sealed by supplying an encapsulant to the cavity through a through opening in the substrate which communicates with the cavity.

Technique for underfilling stacked chips on a cavity MLC module

Growing community of inventors

Lagrangeville, NY, United States of America

Brian C Noble