Freescale Semiconductor,inc.

Samsung Electronics Co., Ltd.

Brian C Grayson

Michael D Snyder

Kevin Michael Lepak

Karthik Sundaram

Paul Edward Kitchin

Rama S Gopal

Arun Radhakrishnan

Murali S Chinnakonda

James C Holt

Leick D Robinson

Kathryn C Stacer

Hao Wang

Benjamin M Menchaca

Matt B Smittle

Gerald Zuraski

Jyotsna Kartha

Dilip Muthukrishnan

Wichaya T Changwatchai

Hassan F Al-Sukhni

According to one general aspect, an apparatus may include a load/store circuit and a region size detection circuit. The load/store circuit may be configured to issue a plurality of store instructions to store data in a memory system. The region size detection circuit may be configured to determine a cache from a plurality of caches to store a stream of store instructions based upon, at least in part, by tracking multiple cache-line address entries in the plurality of store instructions, wherein each address entry is updated at a different frequency.

System and method for store streaming detection and handling

According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.

Pre-fetch chaining

Dynamically predicting a Read-After-Write (RAW) hazard by employing a variable confidence score attributed to a RAW Resynchronization Predictor (RRP) for sampling the RRP at timing periods dynamically adjusted based on the confidence score to optimize prediction of the RAW hazard.

Read-after-write hazard predictor employing confidence and sampling

A cache management system employs a replacement policy in a manner that manages concurrent accesses to cache. The cache management system comprises a cache, a replacement policy storage for storing replacement statuses of cache lines of the cache, and an update module. The update module, comprising access filtering and a concurrent update handling, determines how updates to the replacement policy storage are handled. In a multi-threaded compute environment, a concurrent access to shared cache causes a selective update to the replacement policy storage.

Opportunistic cache replacement policy

A state indicator associated with a cache line is stored, wherein the cache line is one of a plurality of cache lines each associated with a corresponding unique section of a region of system memory. The state indicator comprises a dirty indication indicating that the cache line is a candidate for writing data stored in the cache line to the associated section of the region of system memory. The state indicator is one of a plurality of state indicators each associated with a corresponding cache line. For the region of system memory, a number of the plurality of state indicators that comprises the dirty indication is determined, and if a threshold is exceeded, data stored in a selected cache line is written to the associated section of the region of system memory, and a clean indication is stored in the state indicator corresponding to the cache line.

Writing data to system memory in a data processing system in which cache line states are tracked

A logic block is presented that generates avalanche criterion hash values using minimal logic. The logic block includes a first exclusive-OR function, a second exclusive-OR function, and an OR function. The first exclusive-OR function receives two input bits from a data packet and generates a linear output value based upon exclusive disjunction between the two input bits. The OR function receives two different input bits from the data packet and generates a first nonlinear output value based upon logical disjunction between the two different input bits. The second exclusive-OR function receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value. In turn, the second nonlinear output value is utilized to generate a hash value for the data packet.

Hash function for hardware implementations

Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.

Prefetching using hashed program counter

Growing community of inventors

Austin, TX, United States of America

Brian C Grayson