Compaq Computer Corporation, Inc.

Brian B Tucker

Randy M Bonella

Maria L Melo

Gary W Thome

Brian V Belmont

An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.

Circuit for selectively preventing a microprocessor from posting write

Circuitry which corrects a problem in the 82424TX Cache and Dram Controller (CDC) from Intel with the addition of only minor circuitry which can be used externally or internally and which allows proper operation under all conditions. Combinatorial logic is provided to block the dirty bit provided by the dirty Static Random Access Memory (SRAM) when the processor is performing a noncacheable access as indicated by the Page Cache Disable (PCD) bit. In certain cases the PCD bit is ignored and the stored dirty bit is passed without blocking: when the AHOLD signal is asserted, indicating that an address snoop operation is occurring, and when the BOFF* signal is asserted, indicating that a cache flush or writeback operation is occurring. Thus, the dirty bit provided by the dirty SRAM when the processor is performing a non-cacheable access is selectively blocked in certain instances to ensure cache coherency.

Circuit for masking a dirty status indication provided by a cache dirty

A computer system determines the presence of a device on the system bus that responds to I/O or memory reads by performing an I/O or memory read with data bus pulled to its normally undriven state. If the value returned is other than the data bus' normally undriven value, it is determined that a device is responsive to that I/O or memory read. Otherwise, the system then pulls the data bus to other than its normally undriven state and performs another I/O or memory read. If the value returned is again the value of the data bus' normally undriven state, it is determined that a device is present because it is driving the data bus back to its normally undriven state. Otherwise, it is determined that a device is not driving the data bus in response to an I/O or memory read. Further, the computer system according to the invention makes the determination of whether a device is driving the bus using a comparator to compare the level present on the data bus in response to the I/O or memory reads.

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The Woodlands, TX, United States of America

Brian B Tucker