Texas Instruments Corporation

University of Texas System

Brian Ashley Smith

Haowen Bu

Douglas Ticknor Grider

James Walter Blatchford

Francis Gabriel Celii

Lindsey H Hall

Robert Kraft

Alwin J Tsao

Antonio Luis Pacheco Rotondaro

Pr Chidambaram

Nital S Patel

Lawrence J Overzet

Majid Movahed Mansoori

Juanita DeLoach

Dale R Burrows

Jeffrey S Hodges

Yu-Lun Lin

Nital Patel

The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layerand a hardmask layerlocated over the substratewith plasma, trimming the photoresist layerwith a plasma to create an exposed portionof the hardmask layer, removing the exposed portionwith a plasma to create a trench guide opening, and creating a trenchthrough the trench guide openingwith a plasma.

In situ hardmask pullback using an in situ plasma resist trim process

A method of forming a gate electrode (') for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (), for example formed of silicon-rich nitride, is deposited over a polysilicon layer () from which the gate electrode (&#x2032;) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer () is then formed over the hardmask layer (), and photoresist () is photolithographically patterned to define the pattern of the gate electrode (&#x2032;), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist () to the BARC layer (). The remaining elements of the BARC layer () are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer () by an anisotropic etch of that layer, using the trimmed BARC elements () as a mask. The hardmask layer elements (&#x2032;) then mask the etch of the underlying polysilicon layer (), to define the gate electrodes (&#x2032;), having gate widths that are narrower than the minimum dimension available through photolithography.

Method for patterning sub-lithographic features in semiconductor manufacturing

A method () of forming a transistor includes forming a gate structure () over a semiconductor body and forming recesses () substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown () in the recesses, followed by forming sidewall spacers () over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body () after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

Drive current improvement from recessed SiGe incorporation close to gate

The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.

Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon

The present invention provides a method for determining resist trim times in an etch process. In one embodiment of the invention, the method for determining resist trim times includes obtaining resist profile data and critical dimension (CD) data of a patterned resist layer using a scatterometer, in a step , and then obtaining an estimated trim time of the patterned resist layer using the resist profile data and critical dimension data, in steps

Method for controlling a critical dimension (CD) in an etch process

An apparatus and method for controlling the plasma potential of a plasma within a plasma chamber (50) is disclosed. The apparatus and method utilize a Faraday shielded inductive source antenna (60) to generate the plasma within the plasma chamber (50) and an electrically conductive probe (100) that is inserted into the plasma chamber (50) to regulate the plasma potential. By independent biasing of the conductive probe (100), which regulates the plasma potential, the ion energy distribution at a conductive substrate (150) within the plasma chamber (50) may be controlled.

System for ion energy control during plasma processing

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Plano, TX, United States of America

Brian Ashley Smith