Texas Instruments Corporation

International Business Machines Corporation

Semtech Corporation

Brian Ashley Carpenter

Juan Alejandro Herbsommer

Marie Denison

Osvaldo Jorge Lopez

Jonathan Almeria Noquil

Girish Chandra Johari

Tetsuo Tateishi

Preetam Tadeparthy

Christopher John Sanzo

Russell Alan Resnick

Nitin Kumar Agarwal

Matthew David Romig

Peter S Lee

David Alexander Grant

Andrew Boyce McNeill, Jr

Mark Elliot Andresen

Alok Kumar Lohia

William Todd Harrison

Dattatreya Baragur Suryanarayana

Robert E Reiland

Gary E O'Neil

Thomas H Newsom

Mark G Noll

Biranchinath Sahu

William Walter Vetter

Michael Thomas DiRenzo

Darryl C Newell

Ben A Dowlat

Earl Hardin Booth

Robert Bedford Ferrier

Garry Trevor Tomlins

Joseph Michael Andruzzi

Daragh Padraic MacGabhann

Kevin M Silk

Chester Robert Burroughs

Rhys Philbrick

Rama Venkatraman

Thomas Dale Ivins

Methods and apparatus to provide a high-efficiency drive for a floating gate are disclosed. An example apparatus includes a driver including a supply terminal, the driver configured to output a third voltage corresponding to the supply terminal, the driver to drive a gate of a transistor in a power converter; and a second capacitor to be charged using a first discharging current of a first capacitor and discharged at the supply terminal of the driver, the driver to drive the gate of the transistor based on a second discharging current from the second capacitor.

Methods, apparatus, and system to provide a high-efficiency drive for a floating power device

A voltage converter circuit includes a high side transistor, a high side driver coupled to a control input of the high side transistor, a low side transistor coupled to the high side transistor at a switch node, and a current steering circuit coupled to the control input of the high side and to the switch node. During transition of the high side transistor to an on state, a current from the high side driver initially divides between the control input of the high side transistor and the current steering circuit, and as a voltage on the switch node increases, less of the current from the high side driver flows through the current steering circuit and more of the current from the high side driver flows to the control input of the high side transistor.

Voltage converter with current steering

A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Stacked die power converter

A circuit and method for providing improved load transient response in a DC-DC converter. A DCM modulator is incorporated into the converter controller to generate a DCM enable signal for the driver circuits for the converter. During normal operation, the DCM enable signal will remain in a first state and the driver circuits will operate in a continuous conduction mode. However, upon a load transient, the DCM enable signal will change to a second state and the driver circuits will operate in a discontinuous conduction mode.

Modulation circuit for enhanced load transient response

A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin.

Integrating multi-output power converters having vertically stacked semiconductor chips

Control logic for producing a digital input to a digital-to-analog converter (DAC) in a power converter system. The control logic selects from among a plurality of slew rates during a transition of an output voltage in response to a change in the desired setpoint, so that the output voltage transition follows a desired nominal slew rate. In an initial interval of the transition, a steeper slew rate than the nominal slew rate is selected by the control logic for the digital input to the DAC, until the digital input to the DAC exceeds the nominal slew rate by a first parameter value. At that point, a slew clamp is applied to advance the digital input at the nominal slew rate. Upon the digital input approaching the setpoint value to within a second parameter value, a flatter slew rate than nominal is applied.

Digital pre-compensation for voltage slewing in a power converter

An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin.

A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin.

Integrating multi-output devices having vertically stacked semiconductor chips

A packaged multi-output converter () comprising a leadframe with a chip pad () as ground terminal and a plurality of leads () including the electrical input terminal (); a first FET chip (sync chip,) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal () positioned adjacent to a second drain terminal (), the drain terminals connected respectively by a first () and a second () metal clip to a first () and second () output lead; a second FET chip (control chip,), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip,), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals () of the second and third chips attached onto a third metal clip () connected to the input lead ().

Communications systems and methods for transmitting communications between a charge system and an AC adapter are disclosed. In one embodiment, a communication system comprises an AC adapter disconnect switch that is switchable between coupling and decoupling an AC adapter DC output voltage to the charge system and a charge controller configured to modulate the AC adapter disconnect switch between coupling and decoupling to provide a communication signal to the AC adapter.

Communication systems and methods for transmitting communications between a charge system and an AC adapter

A controller for controlling a power chain in an electronic device can be used in either of two different applications. The first application requires the controller to produce drive signals for driving discrete power MOSFETs within the power chain. The second application requires the controller to produce an output PWM signal to control an integrated circuit having power MOSFETs integrated with MOSFET drivers within the power chain. The controller generally includes a sensor that detects which of the two applications the controller is in. The controller also generally includes outputs that produce, when the controller is in the first application, the drive signals for driving the discrete power MOSFETs. But when the controller is in the second application, one of the outputs is used to produce the output PWM signal for controlling the integrated circuit.

Controlling power chain with same controller in either of two different applications

A converter for a multi-phase current network can include a plurality of current sensors, each of the plurality of current sensors being configured to detect current for a respective phase of the multi-phase network. A current averaging circuit is configured to provide an indication of the average current for the multi-phase network based on the current detected by each of the plurality of current sensors. A modulator is configured to modulate at least one phase of the multi-phase network independently of each other phase of the multi-phase network based on a difference between the current detected for the at least one phase and the average current for the multi-phase network.

Current balancing for multi-phase converters

In one or more embodiments, a switched mode power supply circuit is configured to monitor and control its output voltage during discontinuous conduction mode (DCM) operation, to prevent output over-voltage conditions. For example, in one embodiment, a switched mode power supply circuit is configured to operate selectively in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), and it includes a control circuit that is configured to detect an output over-voltage condition during DCM operation. The control circuit reduces the output voltage of the switched mode power supply circuit responsive to detecting the output over-voltage condition, such as by activating a pull-down device and/or temporarily reverting the switched mode power supply circuit to continuous conduction mode (CCM) operation.

Switched mode power supply method and apparatus

A voltage regulator improves its transient adjustment response by amplifying error in its regulation feedback control path, including any droop-related error. Amplifying the error speeds up the voltage regulator's response to load changes and droop control adjustments by exaggerating the feedback error. Thus, in at least one embodiment, a droop control circuit imparts a droop-related offset between an output feedback signal and a reference signal responsive to a droop adjustment signal, and a response-enhancing amplifier circuit amplifies that offset for input to an error sensing circuit of a regulation control circuit. The gain and frequency response of the response-enhancing amplifier circuit may be set as a function one or more regulation stability criteria, and the response-enhancing method may be adapted to a variety of voltage regulator topologies. Such topologies include, but are not limited to, PWM regulators and hysteretic regulators.

Method and apparatus for enhancing voltage regulator transient response

Aspects for detecting faults in a redundant power converter are described. In an exemplary circuit aspect, a circuit for sensing faults in a redundant power converter includes a first voltage level detection mechanism and a second voltage level detection mechanism. The first voltage level detection mechanism detects a voltage level at a predetermined node relative to a first switch gate voltage during a first switch on-time. The second voltage level detection mechanism detects a voltage at the predetermined node relative to a second switch gate voltage during a second switch on-time, wherein a fault is detected when the voltage level violates a threshold level in one of the first voltage level detection mechanism and the second voltage level detection mechanism.

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Cary, NC, United States of America

Brian Ashley Carpenter