Emc Corporation

Brian Arsenault

Victor W Tung

Rudy M Bauer

Stephen Lawrence Scaringella

William F Baxter

Jeffrey Kinne

Antonio Fontes

Brian Daniel Kennedy

A data storage system having a plurality of disk drive sections, each one of the disk drive sections having a plurality of disk drives. Each one of a plurality of secondary SAS expanders is coupled to a corresponding one of the disk drive sections. Each one of the secondary SAS expanders has: (1) a plurality of first ports each one being connected to a corresponding one of the disk drives in the corresponding one of the plurality of disk drive sections coupled thereto; and (2) a second port. A main SAS expander has: (1) a first port; and (2) N second ports, each one of the N second ports of the main expander being connected to the second port of a corresponding one of the plurality of N secondary expanders. A storage processor is coupled to the second port of the main SAS expander.

Expandable data storage system

A system having a plurality of processors, each one of the processors being adapted to issue a control signal and a processor ID code. Each one of the processors has: a unique, pre-assigned processor ID code, and a common software program. The software program operates to: receive the control signal and the processor ID code from the issuing one of the processors along with an indication of the one of the processors which issued the particular control signal and processor ID code; and test whether the received processor ID code is the same as the processor issuing the command and if so, generate one of the broadcast mode or uni-cast modes; otherwise, generate the other one of the broadcast or uni-cast modes.

System having plural processors and a uni-cast/broadcast communication arrangement

A method and apparatus for controlling the flow of data through director elements of a disk drive controller are responsive to external clock signals to synchronize the internal clock timing of each director. The external clock signals are available over either a first master bus or a secondary master bus, each of the buses being connected to the director element. Each director element has circuitry which monitors the occurrence of clock pulses over the buses as well as circuitry for switching, upon the occurrence of a failure of clock pulses on the master bus, from the master bus to the secondary bus for the receipt and resynchronization of clock pulses.

Disk drive controller for controlling data flow therethrough by switching to secondary bus to receive clock pulses when a failure on master bus is detected

A system having a memory with a plurality of contiguous processor memory regions and a plurality of processors. Each one of such processors is associated with a corresponding one of the processor memory regions. Each one of such processors provides a plurality of sets of successive processor addresses. The addresses in each one of such sets has a successive series of used addresses and a successive series of reserve addresses. The last used address in each one of the sets is separated from the first used address in the next successive set of addresses by a gap of addresses, G. A common address translator is fed by virtual addresses and maps the virtual addresses fed thereto to the memory addresses, such mapping being in accordance with the gap G to map each one of the sets of used processor addresses provided by each of the processors into the corresponding one of the contiguous processor memory regions.

Address management for a shared memory region on a multi-processor controller board

A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.

System and method for maintaining synchronization in a computer storage system

A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface includes a system memory comprising a pair of system memory sections. Each one of the system memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A pair of system busses is provided, each one of the pair of system busses being coupled to a corresponding one of the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus. The directors are configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory. The directors are configured to place the system in a dual-write mode, and in such mode, store therein a burst of the data to be transferred between the host computer and the bank of disk drives, transfer such stored burst of data sequentially to the pair of system busses, and enable both of the system memory sections coupled to such pair of system busses to have written therein, at the same one of the addressable locations, the same burst of data transferred sequentially to the pair of system busses.

Data storage system

A method and a control device is provided for upgrading computer system hardware, for example, on a printed circuit board, with system revision information. The method includes receiving, a serial data stream having data bits associated with the system revision information through a serial input of the control device, determining the start of the data bits, and storing at least a portion of the data bits associated with the system revision information within a read-only register of the control device.

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Leicester, MA, United States of America

Brian Arsenault