Analog Devices,inc.

Analog Devices Global

Brian Anthony Moane

John Twomey

David J Clarke

Colm Patrick Ronan

Liam Joseph White

Javier Alejandro Salcedo

Patrick Martin McGuinness

Edward John Coyne

William Allan Lane

Denis Ellis

Donal McAuliffe

Seamus Paul Whiston

Michael G Tuthill

Patrick J Meehan

Michael P Lynch

Michael P Daly

Stephen Denis Heffernan

Kieran K Heffernan

Denis J Doyle

Michael Lynch

Brian Sweeney

Keith A Moloney

George Francis Clernon

James Scanlon

An integrated circuit is provided in which a surge protector, protecting against modest over-voltage events which may contain a lot of energy, and an electrostatic discharge (ESD) protector, protecting against high voltage events that may contain only a little energy, are provided within the integrated circuit package. The two types of protectors may protect against different types of electrical events.

Chip including over-voltage and surge protection

A transformer based digital isolator is provided that has improved immunity to common mode interference. The improved immunity is provided by placing the transformer in association with an H-bridge drive circuit, and taking additional effort to tailor the on state resistance of the transistors to control a common mode voltage at the transformer.

Galvanically isolated data isolator with improved common mode transient rejection

A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.

Overvoltage protection device and method

A voltage regulator receives an unregulated DC input voltage supply and provides a regulated DC output voltage. A primary pass element and an external resistor are located in a primary current path through which a load current flows from the input terminal to the output terminal. The voltage regulator includes two control circuits that control the impedances of two pass elements. Power dissipation can be improved and the dropout voltage can be reduced by maintaining the voltage on an internal node of the voltage regulator.

Voltage regulating circuit and a method for producing a regulated DC output voltage from an unregulated DC input voltage

Bi-directional blocking voltage protection devices and methods of forming the same are disclosed. In one embodiment, a protection device includes an n-well and first and second p-wells disposed on opposite sides of the n-well. The first p-well includes a first P+ region and a first N+ region and the second p-well includes a second P+ region and second N+ region. The device further includes a third P+ region disposed along a boundary of the n-well and the first p-well and a fourth P+ region disposed along a boundary of the n-well and the second p-well. A first gate is disposed between the first N+ region and the third P+ region and a second gate is disposed between the second N+ region and the fourth P+ region. The device provides bi-directional blocking voltage protection during high energy stress events, including in applications operating at very low to medium swing voltages.

Bi-directional blocking voltage protection devices and methods of forming the same

An output stage interface circuit for interfacing with a data bus, comprising first and second rails for receiving respectively a high voltage and a low voltage from a power supply; a data output terminal; a first main switch element coupled between said terminal and the first rail and comprising a first main MOS device having a gate and an independently configurable back gate, and responsive to a first data control signal applied to the gate pulling the voltage on the data output terminal toward the first rail voltage; and a first control circuit responsive to the voltage on said terminal being pulled from a first state across a first voltage reference to a second state for coupling said back gate to said terminal and permitting coupling of the gate of said MOS device to said terminal, the first main MOS device presenting a high impedance on the terminal when its voltage is pulled to the second state.

Output stage interface circuit for outputting digital data onto a data bus, and a method for operating an output stage interface circuit

A voltage level shifting circuit () for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit () comprises a first resistive voltage divider circuit () coupled between a first input terminal () and a voltage reference terminal () for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit () coupled between a second input terminal () and the voltage reference terminal (). The differential signal is applied to the first and second terminals (), and the level shifted differential signal is produced on first and second output taps () of the first and second resistive voltage divider circuits () with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (). First and second high frequency low impedance circuits () couple the first and second input terminals () to the first and second output taps () to provide respective direct current blocked high frequency low impedance paths for the differential signal to first and second differential inputs () of the differential input buffer circuit () for minimizing propagation delays resulting from low pass filters created by the interaction of the first and second resistive voltage divider circuits () with first and second intrinsic input capacitance (C,C) coupling the first and second differential inputs () of the differential input buffer circuit () to ground.

Voltage level shifting circuit, a differential input stage circuit, and a method for providing a level shifted differential signal to a differential input buffer circuit

An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node. In a second aspect to the invention, a further region of heavily doped P-type material is formed in the first lightly-doped region of P-type material. In a third aspect to the invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this third aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node, with a further region of heavily doped P-type material formed in the first lightly-doped region of P-type material. Accordingly, an input protection device for protecting pins of an integrated circuit is described having both bipolar and unipolar characteristics. The input protection device may be constructed as a discrete device or as part of an integrated circuit and provides for breakdown voltages in excess of a supply voltage to an integrated circuit. The characteristics, in particular the breakdown voltage, of the input protection device are alterable by adjusting its layout, in contrast to a known method of altering such characteristics by altering doping levels.

SCR cell for electrical overstress protection of electronic circuits

A control circuit (,) for controlling a FET (,) for outputting a 3.3 volt or a regulated 1.5 volt output to an AGP bus on a PC motherboard in response to a TYPEDET signal being applied to a control terminal (,) of the control circuit (,) through an input (,) of a voltage divider circuit (,). The TYPEDET signal is received from a video card receiving slot and indicates the type of video card in the slot of the motherboard. An amplifier (,) outputs a control signal to the gate of the FET (,) for either disabling the FET (,), or enabling the FET (,) to output the 1.5 volt or the 3.3 volt outputs. A decoding circuit (,) decodes the state of the control terminal (,) and controls the amplifier (,) to disable the FET (,) during power up. When the TYPEDET signal of zero volts, the FET (,) is operated to output the 1.5 regulated voltage output. When the TYPEDET signal is floating, the FET (,) outputs the 3.3 source voltage. When the voltage on the control terminal (,) is not connected to the voltage divider circuit (,), the FET (,) is operated to output the 1.5 regulated voltage.

Control circuit for controlling a semi-conductor switch for selectively outputting an output voltage at two voltage levels

A high swing interface output stage integrated circuit for interfacing a data communications device with a data bus which may operate at voltage ranges outside the supply voltage of the interface circuit. An output terminal of the integrated circuit is coupled to a positive supply rail of the circuit through a substrate NPN transistor, and to a ground rail through first and second NMOS FETS. A third MOS FET also formed is coupled between the common connection of the first and second NMOS FETS and the gate of the second NMOS FET for holding the second NMOS FET off in the event of the voltage on the output terminal being driven below the ground voltage of the circuit. Other NMOS and PMOS FETS in the circuit control the operation of the circuit for determining the high and low states of the voltage on the output terminal. The interface circuit presents either a high impedance or a current limiting impedance to the output terminal in the event of the output terminal voltage being driven outside the supply voltage of the circuit.

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Raheen, Ireland

Brian Anthony Moane