Applied Micro Circuits Corporation

Brian Abernethy

Yehuda Azenkot

Simon Pang

Hongming An

Bruce H Coy

Michael Hellmer

A method and device are disclosed for providing an ultra low-noise hand gap voltage reference. The method detects a first voltage drop across a first diode reference, and a second voltage drop across a second voltage reference that includes a second diode. The first and second voltage drops are compared. Temperature compensation currents are supplied to the first diode reference and second voltage references in addition to constant currents, where the constant currents have the same value across a first temperature range. As a result of the constant current, a minimal amount of temperature compensation current is required. Alternatively stated, temperature compensation current is provided having a rate of change greater than PTAT. In response to comparing the first voltage drop to the second voltage drop, a true sub-volt hand gap voltage is supplied across a third voltage reference including a diode, that is constant across the first temperature range.

Ultra low-noise true sub-volt band gap

Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.

Fractional phase-locked loop with dynamic divide ratio adjustment

A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.

Clock generation for N.5 modulus divider

A system and method are provided for reducing the threshold bias offset voltage in a comparator, by canceling and bypassing the bias offset current errors. The comparator system comprises amplification stages with bias cancellation circuitry and a threshold setting circuit. The bias offset current cancellation circuit is used to cancel the base current of differential amplifier input emitter follower. The bias offset current cancellation circuit also cancels the loading effect of amplifier input emitter-follower driving stage. The threshold offset voltage is further reduced by the threshold setting circuit. The threshold-setting circuit includes two integrators and a unit gain operation amplifier. The integrators have the input accept a single-ended input signal, an output connected to the negative input of the comparator, and an output connected to the unit gain operational amplifier, whose output is connected to the negative input of the comparator.

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Escondido, CA, United States of America

Brian Abernethy