3Com Corporation

Brian A Petersen

David R Brown

W Paul Sherer

Lai-Chin Lo

Richard S Reid

Scott A Emery

Early initiation of transmission of data in a network interface that includes a dedicated transmit buffer is provided in a system which includes logic for transferring frames of data composed by the host computer into the transmit buffer. The amount of data of a frame which is downloaded by the host to the transmit buffer is monitored to make a threshold determination of an amount of data of the frame resident in the transmit data buffer. The network interface controller includes logic for initiating transmission of the frame when the threshold determination indicates that a sufficient portion of the frame is resident in the transmit buffer, and prior to transfer of all of the data of the frame into the transmit buffer. The monitoring logic includes a threshold store, which is programmable by the host computer for storing a threshold value. Thus, the threshold value may be set by the host system to optimize performance in a given setting.

Method for automatic initiation of data transmission

A mechanism is provided that allows partial reading of storage locations, such as statistics counters, by providing a temporary read data storage latch on a peripheral device. The latches are updated with fresh data from an address storage location whenever any one of the following conditions is met:

System for reading dynamically changing data supporting partial reads of

A mechanism is provided that allows partial reading of storage locations, such as statistics counters, by providing a temporary read data storage latch on a peripheral device. The latches are updated with fresh data from an address storage location whenever any one of the following conditions is met: 1. The address accessed by the host differs from the previous access; 2. The host has written to the device prior to the current read; or 3. When accessing the same location sequentially, one or more bytes of the second read have already been read by the host in a previous read. These rules allowed for byte- or word-wise write/read/verify cycles; byte- or word-wise reads of dynamic data; and byte, word, or double-word with polling of registers. With this mechanism, it is impossible for the host to erroneously end up with 01ff (hex) as it reads a four byte register a byte at a time when the register increments from 00ff to 0100 between the sequential reads.

Network interface card for reading dynamically changing data

System for reading dynamically changing data

Indication and interrupt signals generated by a network adapter representing asynchronous events are managed by a host system. The network adapter includes a first mask logic for selectively disabling the indication signals from being stored in a first memory location by the host writing to a first mask register. A second mask logic which is coupled to the first memory location also selectively disables the indication signals from being stored in a second memory location creating two levels of status information. The indication signals may also be disabled from being stored in the second memory location responsive to the host writing to a second mask register. The first memory location may be read from the host in order to determine whether a network event occurred during an interrupt service routine, while interrupt means generates an interrupt signal to the host responsive to the value in the second memory location. A third level of control is provided by an internal counter which allows for automatic enabling and/or disabling of a plurality of indications and interrupts with and without explicit commands in the host driver subroutines.

Network adapter with an indication signal mask and an interrupt signal

A data aligner transfers data from an input having N+1 byte lanes to an output having N+1 byte lanes. The data aligner includes a write data aligner and a read data aligner. The write data aligner includes a write shifter coupled to the N input byte lanes and a stage having N selector/registers S1(i). The N selector/registers each have a queuing register R(i) and bypass multiplexer M(i). The N selector/registers are coupled to the N output byte lanes. The write shifter and N selector/registers S1(i) are coupled to a control circuit. The read data aligner includes a stage having N selector/registers S2(i) and a read shifter. The S2(i) selector/registers are coupled to N+1 byte input lanes with the S2(i) outputs coupled to the N read shifter inputs. The read shifter outputs are then coupled to the N+1 output byte lanes. Finally, a control circuit is coupled to the selector/registers S2(i) and read shifter.

Read and write data aligner and method

Apparatus for automatic initiation of data transmission

A data path aligner transfers data from an input having N byte lanes with byte enable bits to an output having N byte lanes. The aligner includes first stage having N-1 selector/registers, and a second stage having N selector/registers. Each of the N-1 selector/registers S1(i) in the first stage has inputs including input lanes L(j) for j going from i+1 to N. Each of the selector/registers S2(i) in the second stage has inputs including input lanes L(k) for k going from i to 0, and for selector/registers S2(i) for i less than or equal to N-2, the inputs include the output of a first stage selector/register S1(i). The outputs of the second stage selector/registers supply data selected from the respective inputs to output segment lanes. All of these selector/registers are controlled by a common select signal derived from a data path offset, and all selector/registers are clocked by a common clock.

DMA data path aligner and network adaptor utilizing same

A computer bus adapter device which is coupled to a true parallel computer bus is automatically set to a pre-determined configuration in response to configuration data provided to the bus by a host process. During a set-up portion of an initialization procedure, the adapter device recognizes a data sequence and uses information based on the recognized data sequence to configure itself to respond to its host process. In a specific embodiment, the desired configuration information is stored in non-volatile storage associated with the host process, such as a magnetic file or a non-volatile random access memory.

Method for configuring a computer bus adapter circuit board without the

Combined indication signals of data block transfers are generated by a device which reduces the number of interrupts to a host processor. The reduction in the number of interrupts enhances host system performance during data block transfers. An embodiment of the device may be a network adapter comprising network interface logic for transferring a data frame between a network and a buffer memory and host interface logic for transferring a data frame between a buffer memory and a host system. The network adapter further includes threshold logic for generating an early receive indication signal when a portion of the data frame is received. Indication combination logic delays the generation of a transfer complete interrupt to slightly before the expected occurrence of the early receive indication. The host processor is able to service both the transfer complete indication and the early receive indication in a single interrupt service routine caused by the transfer complete indication.

Device with host indication combination

Optimized indication signals of a completed data frame transfer are generated by a network adapter which reduces host processor interrupt latency. The network adapter comprises network interface logic for transferring the data frame between the network and a buffer memory and host interface logic for transferring the data frame between the buffer memory and the host system. The network adapter further includes threshold logic where a threshold value in an alterable storage location is compared to a data transfer counter in order to generate an early indication signal. The early indication signal may be used to generate an early interrupt signal to a host processor before a transfer of a data frame is completed. The network adapter also posts status information status registers which may be used by the host processor to tune the timing of the generation of the network adapter interrupt signal.

Network adapter with host indication optimization

A network interface controller controls communication between a host system and a network transceiver coupled to a network comprises a memory outside of the host address space in which receive and transmit buffers are managed, host interface logic emulating memory mapped registers in the host address space, for transferring data between the host address space and the buffer memory, and network interface logic coupled with the network transceiver, for transferring data between the buffers in the buffer memory and the network transceiver. The buffer memory includes a transmit descriptor ring buffer, transmit data buffer, transfer descriptor buffer, and receive ring buffer all managed by operations transparent to the host.

Growing community of inventors

Los Altos, CA, United States of America

Brian A Petersen