British Aerospace Public Limited Company

Brian A Johnson

John A Geen

John R Guppy

Paul A Findlay

For more convenient mechanisation, the modulo m reduction of a binary number P can be carried out by conditionally summing the modulo m reductions of a power series of two and then modulo m reducing the sum. The modulo m reductions of the series, called the `residues` of the series, can be pre-calculated and stored but this may be inconvenient if they are long in terms of numbers of bits. Herein, the residues are calculated in sequence by a recursive process, each residue being calculated from the next preceeding one, this leading to a `serial` arrangement for generating the residues which can be incorporated into a serial modulo m reduction unit. Such a serial modulo m reduction unit is convenient for implementation as an integrated circuit especially as part of an overall circuit for encryption and decryption of digital signals.

Digital signal processing

Analog-to-digital converters are subject to errors including the known half least significant bit quantization error and also bit weighting errors due to lack of an ideal binary relationship between the transition points of all the bits. The known statistical average error reduction method in which a relatively small dither component is added to the analog input signal can only fractionally reduce overall error and has little effect on bit weighting errors. Herein the analog signal is added to a dither signal, for example a ramp signal, which varies through half the peak to peak digitization range of the converter so that irrespective of the input signal all output signal bits, other than the most significant bit, are 'on' for one half of the sampling period. The result is that all the less significant bit errors are cancelled leaving only the easily compensated most significant bit error. A random component can be added to the dither signal to reduce the quantization error.

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Hatfield, United Kingdom

Brian A Johnson