Advanced Micro Devices Corporation

Ati Technologies Ulc

Ati Technologies Inc.

Brian A Buchner

Vineet Goel

Mangesh P Nijasure

Jason David Carroll

Rex Eldon McCrary

Todd Martin

Ralph Clay Taylor

Jeffrey T Brady

Randy Wayne Ramsey

Anthony P DeLaurier

A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.

Load balancing for optimal tessellation performance

Disclosed herein methods, apparatuses, and systems for performing graphics processing. In this regard, a processing unit includes a tessellation module and a connectivity module. The tessellation module is configured to sequentially tessellate portions of a geometric shape to provide a series of tessellation points for the geometric shape. The connectivity module is configured to connect one or more groups of the tessellation points into one or more primitives in an order in which the series of tessellation points is provided.

Tessellation engine and applications thereof

Apparatus and systems utilizing fixed point filtering to perform floating point texture filtering. A texture pipe unit consisting of a texture addressing unit, texture cache unit, and texture filter unit accepts texture requests for a specified pixel from a resource and returns formatted bilinear filtered results based on the specific pixel's corresponding four texels. The texture filtering unit consists of a pre-formatter module, interpolator module, accumulator module and a format module. The pre-formatter module accepts texel data in a floating point or fixed point format. However, if the data is in a floating point format the pre-formatter module converts the floating point data into a normalized fixed point data format whereby the interpolator module may perform its bilinear interpolator functions using standardized fixed point systems and apparatus without necessitating the use of floating point arithmetic units. A method utilizing fixed point filtering to perform floating point texture filtering is also presented.

Floating point texture filtering using unsigned linear interpolators and block normalizations

Tessellation triangles, which are used to model three-dimensional surfaces in computer-generated graphics, can be more efficiently calculated by retrieving tessellation triangle vertices and Bezier-function coefficients using a single, two-part address.

Method and apparatus for triangle tessellation

Apparatus and methods for a bilinear filter system comprising a pre-formatter module, a bilinear module, an accumulator module, and a format module. The pre-formatter module is configured to receive texel data and convert it to a normalized fixed point format. The bilinear module is dynamically reconfigurable to perform an interpolation or an extended precision interpolation on the normalized fixed point texel data from the pre-formatter module and generate re-normalized floating point texel data. The interpolator analyzes the exponent range of fixed point texel data from the pre-formatter module to determine if an extended precision calculation is appropriate. The accumulator module is configured to accumulate floating point texel data from the bilinear module to achieve the desired level of bilinear, trilinear, and anisotropic filtering. The format module is configured to convert texel data from the accumulator module into a standard floating point representation.

Dynamically configurable bilinear filtering system

An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative to execute a memory request. The method and apparatus further includes a memory interface coupled to the cache controller, the memory interface operative to retrieve a plurality of requested data. The method and apparatus further includes a request processor coupled to the cache controller, the memory interface and the memory access request generator. The request processor is operative to receive a plurality of requested data and thereupon generate a plurality of parallel data outputs therefrom.

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Oviedo, FL, United States of America

Brian A Buchner