Lenovo (singapore) Pte. Ltd.

International Business Machines Corporation

Brian A Baker

Michael DeCesaris

Jeffrey Ross Hamilton

Douglas R Oliver

Luke David Remis

Christopher Landon Wood

William Mark Megarity

Challis Llewellyn Purrington

Ivan R Zapata

Pravin S Patel

Justin Potok Bandholz

Sumeet Kochar

Kenneth Scott Seethaler

James Edward Hughes

Christopher Collier West

Thomas Dixon Pahel, Jr

Henry Gaines McMillan

Mark Allan Casparian

Victor A Stankevich

William H Cox, Jr

Gregory J Zandt

Reconfigurable processors and methods for collecting computer program instruction execution statistics are disclosed. According to an aspect, a method includes providing a reconfigurable processor configured to execute a set of central processing unit (CPU) instructions that each have a function. The method also includes modifying the function of one or more of the CPU instructions that identifies an instruction address and a destination address pair of the CPU instruction(s) based on a defined test case. Further, the method includes using the reconfigurable processor to execute the set of CPU instructions. The method also includes identifying an instruction address and destination address pair of the CPU instruction(s) having the modified function when the CPU instruction(s) having the modified function is executed during execution of the set of CPU instructions.

Reconfigurable processors and methods for collecting computer program instruction execution statistics

Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit ('CPU') sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output ('I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.

Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit ('CPU') sockets

Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit ('CPU') sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, error characteristics associated with each available CPU, wherein the error characteristics associated with each available CPU include error information for computing devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the error characteristics associated with each available CPU and a predetermined error tolerance policy, a target CPU to utilize as a boot CPU.

A chip package comprises: an IC substrate, wherein the IC substrate comprises at least one electronic device; a photovoltaic cell, wherein the photovoltaic cell generates an electrical current when exposed to light; a light blocking shield, wherein the light blocking shield prevents light from striking the photovoltaic cell only while the chip package is mounted on a circuit board, and wherein the light blocking shield ceases to prevent light from striking the photovoltaic cell upon the chip package being dismounted from the circuit board; and a disabling logic, wherein the electrical current, which is generated by the photovoltaic cell in response to the chip package being dismounted from the circuit board, causes the disabling logic to disable the IC substrate.

IC chip package disabling device

A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the processor by over-reporting the amount of current drawn by the processor to the current monitoring feedback line to the processor, wherein the processor uses the over-reported current to maintain operation of the processor within performance specifications of the processor. An automatic calibration routine may be used to determine nominal amounts of current over-reporting that may be used to prevent the processor performance from exceeding the maximum turbo mode. In one embodiment, a digital potentiometer is included in the voltage regulator circuit to over-report the current as instructed.

Operating processor below maximum turbo mode frequency by sending higher than actual current amount signal to monitor

Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Printed circuit boards for countering signal distortion

An embodiment of the present invention is directed to a memory module connector having a pivotable air baffle that controls airflow at the memory module connector. When the memory module connector is occupied by a memory module, the air baffle may rest on an upper edge of the memory module, substantially parallel to the system board and in general alignment with the airflow. When the memory module has been removed, the air baffle may be pivoted downward toward the connector base and into the airflow, to offset the reduction in airflow impedance caused by the removal of the memory module from the memory module connector.

DIMM connector and memory system with compensated airflow impedance

A method of powering an audio output device of a computer system, by determining whether a passive or active audio output device is connected to an audio output jack of the computer system and, based on this determination, providing an appropriate power level to the audio output jack. For example, if the determination is made that a passive audio output device is connected to the audio output jack, then a 3-watt power signal is applied to the audio output jack, but if the determination is made that an active audio output device is connected to the audio output jack, then a &#xbc;-watt power signal is applied to the audio output jack. The type of audio output device present may be determined by sensing an impedance at the audio output jack. This sensing may be performed by comparing a load voltage associated with the impedance to a reference voltage. The output of a switch device (multiplexer) having a first input from an AC97 audio codec and headphone amplifier and a second input from a passive speaker amplifier is selectively controlled by the sensing circuit.

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Raleigh, NC, United States of America

Brian A Baker