Qualcomm Incorporated

Brett Patrick Delaney

Zhiqin Chen

Julian Puscar

Burcin Serter Ergun

A clock generation circuit has a voltage-controlled oscillator that includes a first transistor pair coupled in series between a power rail and ground, a replica transistor pair coupled in series between a reference node and ground, a current source having an output coupled to the reference node. The current source is coupled to a control signal that determines amplitude of current flowing through the replica transistor pair. A voltage regulator has an input coupled to the reference node and an output coupled to the power rail. The voltage regulator is configured to maintain the power rail at a voltage level defined by the voltage level of the reference node. Each transistor in the replica transistor pair is collocated on an integrated circuit with and has a same type as a corresponding transistor in the first transistor pair.

Power supply calibration for voltage controlled oscillators

A method for calibrating a phase locked loop (PLL) includes counting cycles of an output clock signal generated by the PLL until early phase lock signal is asserted when the cycles of the output clock signal counted within a first duration of time differ from a first target value by no more than a first maximum difference, counting cycles of the output clock signal until final phase lock signal is asserted when the cycles of the output clock signal counted within a second duration of time differ from a second target value by no more than a second maximum difference, the second duration of time being greater than the first duration of time, and using the output clock signal to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.

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San Diego, CA, United States of America

Brett Patrick Delaney