Uniquify, Incorporated

Brett Murdock

Venkat Iyer

Jung Gu Lee

A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

Continuous adaptive data capture optimization for interface circuits

A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.

A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method and a first set of values is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, establishing a second set of values. Several fringe timing points are sampled. A drift amount is compared with a drift correction threshold value and the first optimal sampling point is shifted in time by the drift amount to revise the first optimal sampling point.

A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0.

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San Jose, CA, United States of America

Brett Murdock