Motorola Corporation

Other

Brett L Lindsley

Ira A Gerson

Richard J Vilmur

David E Borth

Stephen N Levine

Bhavan Gandhi

Zhu Li

Uri Dayan

Moshe Tarrab

Cheung Auyeung

Philip J Smanski

Margot Karam

Reginald JuVann Hill

Eric S Collins

Darleen J Stockley

Joseph J Barlo

A digital signal processor operates in conjunction with a scheduler hardware module and a scheduler software module in executing a highest priority runnable event among a plurality of events. The scheduler hardware module communicates an interrupt request signal to the DSP that is indicative of any change in a highest priority runnable event. The scheduler software module is executed by the DSP in response to the interrupt request signal indicating a change in highest priority runnable event. An execution of the scheduler software module by the DSP implements one of a various modes of an interrupt request routine.

Programmable scheduler for digital signal processor

A search system () for a database () including records having a multiple disparate types of media is provided. The search system supports queries, that include different types of search criteria, including content based retrieval search criteria. A fuzzy logic method () is provided for effectively combining the results of different types of search criteria. The fuzzy logic method also allows confidence levels entered by the user for search criteria to be considered in combining results. Retrieval relevance values for documents for at least some search criteria are used in the fuzzy logic method. For content based image retrieval searches, the retrieval relevance values are computed by mapping a distance between quantitative characterizations of a search basis image, and other images into a finite range.

Method for fuzzy logic rule based multimedia information retrival with text and perceptual features

The present invention provides a method, an article of manufacture and a multi-tasking, preemptive, priority based operating device for acceleration of operating system functions using a host processor and a task scheduling accelerator. The host processor processes a plurality of tasks and receives interrupts and uses a predetermined task scheduling accelerator interrupt service routine for responding to the task scheduling accelerator. The task scheduling accelerator is coupled to the host processor and is used for efficiently accelerating real time multi-tasking decisions using scheduling decisions responsive to tasks in the host processor.

Method, device and article of manufacture for efficient task scheduling in a multi-tasking preemptive priority-based real-time operating system

The present invention provides a task scheduling accelerating method, device and article of manufacture for determining and controlling multi-tasking. The device includes a synchronous task command interface for receiving commands from tasks on the host processor; an asynchronous task command interface for receiving commands from tasks and interrupt service routines on the host processor; an interrupt service routine interface for specifying and controlling a task switch; a semaphore post queue interface for specifying and determining a status of a data queue stored in the host processor; a status register for specifying a status of the task scheduling accelerator device; a computational unit for computing task scheduling decisions; and a bus for moving data between registers/interfaces and the computational unit.

Method, device and article of manufacture for implementing a real-time task scheduling accelerator

An arbitration and task switching technique in a real-time multiprocessor data processing system (20) having a common bus (32) and a segmented shared memory (30), where fullness of memory segments of the shared memory (30) is used as a measurement for arbitration and task switching priorities. A bus request mechanism in each of the processors dynamically calculates normalized priority values based on relative needs across the system (20). The normalized priority calculation is based on monitoring the fullness of memory segments of the shared memory (30) associated with each processor (24, 26, 28) of the system (20). Using this normalized priority calculation, the bus access order and bus bandwidth are optimally allocated according to tasks executed by the processors (24, 26, 28). Also, the normalized priority calculation and a preprogrammed threshold is used to control task switching in the multi-processor system (20).

Dynamic bus arbitration priority and task switching based on shared

The present invention provides a method, device and article of manufacture for efficient transfer of data items between a host processor and an external device. The host processor is coupled to external queue pointers and is used for queuing a plurality of data items and transferring the plurality of data items to the external device using an interrupt service routine unit. The external device is coupled to the host processor and is used for storing and incrementing or decrementing the external queue pointers, and processing the data items.

Data transfer using software interrupt service routine between host

The present invention is method and apparatus for preventing overflow and underflow of an encoder buffer in a video compression system. A virtual buffer is created in a rate controller to model the decoder buffer fullness (102). A sequence of bits is generated by an encoder (104). The encoder is controlled by the rate controller to prevent a decoder buffer underflow and overflow. Then, the sequence of bits is received by the encoder buffer to produce a bitstream (106). The bitstream corresponds to an instantaneous channel bitrate. The bitstream is transmitted from the encoder buffer to a decoder buffer following a delay (108). The delay is controlled by a rate controller to synchronize an encoder buffer fullness with a virtual buffer fullness (110). The synchronization prevents overflow and underflow of the encoder buffer.

Method and apparatus for preventing overflow and underflow of an encoder

A method and device are provided for processing an input value to provide an output inverse trigonometric function value of the input value. It substantially comprises a method and device for modifying the input value to obtain an approximation value, determining at least one correction factor, generating at least one intermediate function value, being substantially an inverse trigonometric function value of the approximation value, and combining the intermediate function value with at least one correction factor to determine an output inverse trigonometric function value.

Device and method for evaluating inverse trigonometric functions

A high-speed processor utilizes combinational logic and range limitation for a modified input value to increase efficiency in convergence factor determination for convergent division and square root computation. An input value is modified to a value in a limited range, which is then partitioned into two subdivisions. By utilizing these two groupings, the processing platform minimizes time consumption in conversion factor determination by inverting selected binary bits to form a modified factor and utilizes that modified factor to facilitate high-speed convergence factor computation.

Method and processor for high-speed convergence factor determination

A logarithm of an input value is computed utilizing a function generator to generate a first logarithm of an approximation value of the input value, scaled to a natural logarithm value where the first logarithm is not a natural base logarithm, and then combined with a correction value, obtaining a natural base logarithm of the input value. An error value, related to the input value and the approximation value, is generated and is utilized in a specified power series to determine the correction value. The natural base logarithm obtained is scaled by a natural base logarithm of a desired base of a desired output logarithm, thereby determining the desired output logarithm of the input value that has the desired base.

Device and method for evaluating logarithms

A method and apparatus utilizes 'Lindsley's Law,' a polynomial convergence algorithm, suitable even for high convergence rates, to implement more efficient reciprocal j.sup.th root, and hence, j.sup.th root itself, computations of desired inputs. The invention emphasizes multiplication, instead of addition, as the iterative operator, thereby reducing error at a rate relative to a power of a selected convergence rate.

Method and apparatus for high speed determination of j.sup.th roots and

A method and device are provided for processing an input value to provide an output trigonometric function value of the input value. It comprises a method and device for modifying the input value to obtain an approximation value, determining an error value with respect to the approximation value, generating first and second function values with respect to the approximation value, the first and second function values typically being trigonometric function values and typically being obtained from a memory device, determining at least one correction value utilizing a predetermined number of terms of at least one power series, and combining the at least one correction value with the first and second function values to determine the output trigonometric function value.

Device and method for evaluating trigonometric functions

A method and apparatus are described for processing an input value to provide an output exponential value of a desired base raised to the power of the input value. The method includes, and the apparatus included hardware for implementing, the steps of adjusting the input value relative to the input value, a predetermined base of a first exponential value, and the desired base of the output exponential value to obtain a first scaled value, modifying the scaled value to obtain an approximation value, determining the first exponential value of the approximation value, generating an adjusted error value relative to the first scaled value, the approximation value, and a logarithm of the predetermined base of the first exponential value, determining a correction value for the first exponential value and combining the first exponential value with the correction value to obtain, substantially, the output exponential value having the desired base raised to the power of the input value.

Device and method for evaluating exponentials

A channel bank speech synthesizer for reconstructing speech from externally-generated acoustic feature information without using externally-generated voicing or pitch information is disclosed. An N-channel pitch-excited channel bank synthesizer (340) is provided having a first low-frequency group of channel gain values (1 to M) and a second high-frequency group of channel gain values (+1 to N). The first group controls a first group of amplitude modulators (950) excited by a periodic pitch pulse source (920), and the second group controls amplitude modulators excited by a noise source (930). Both groups of modulated excitation signals are applied to the bandpass filters (960) to reconstruct the speech channels, and then combined at the summation network (970) to form a reconstructed synthesized speech signal. Additionally, the pitch pulse source (920) varies the pitch pulse period such that the pitch pulse rate decreases over the length of the word.

Method and apparatus for synthesizing speech without voicing or pitch

A reliable method for terminating a telephone call is disclosed using a specific sequence of steps performed by the hands-free control system. The invention requires that the call terminating command sequence be recognized as: (1) two separate speech utterances (e.g., TERMINATE and CONVERSATION); (2) in proper sequence (e.g., TERMINATE first, then CONVERSATION); (3) with a maximum pause time interval between the end of the first utterance and the start of the second utterance (e.g., 300 milliseconds); and (4) which meet predefined speech recognition matching criteria. Moreover, the present invention provides the user with a procedure to continue the telephone call in progress should the speech recognizer false, or if the user did not intend to speak the proper command. As a result, present invention enables a user to disconnect a telephone call by voice command with a high degree of reliability, even under high ambient noise conditions.

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Highwood, IL, United States of America

Brett L Lindsley