Microsoft Technology Licensing, LLC

Micron Technology Incorporated

Brett Kenneth Dodds

Terry M Grunzke

Debra M Bell

Majid Anaraki Nemati

Joshua E Alzheimer

Aaron Jannusch

Scott Eugene Smith

Monish Shantilal Shah

James S Rehmeyer

Anthony D Veches

Emily Nicole Wilson

Scott E Smith

Libo Wang

Daniel Sebastian Berger

Di Wu

John A Strange

Ramakoti R Bhimanadhuni

Pallavi Baral

Bhuvan Malladihalli Shashidhara

Peter Hanpeng Jiang

Jasmine Grace Schlichting

Michael Wayne Stephenson

Farah Farzana

Sebastien Nathan R Levy

Josh Charles Moore

Ahu Oral

Arhatha Bramhanand

Juan Arturo Herrera Ortiz

Christina Margaret Tobias

Charlotte Gauchet

The described technology provides a multi-level error correction method, including encoding data received from a double data rate (DDR) memory by performing primary coding to generate transitional symbols, wherein the primary coding comprising at least one of cyclical redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding, performing a secondary coding on the transitional symbols to generate inner codes, the inner codes comprising code 1 parities generated from the transitional symbols and code 2 parities generated from the transitional symbols and metadata stored on the DDR memory, wherein the secondary coding comprising Reed Solomon (RS) encoding, and saving the inner codes on parity bit storage locations on a die of the DDR memory.

Error correction using on-die parity bit storage and transitional signals

A method, computer program product, and computing system for generating first encoded data by performing a first encoding of data included within each of a plurality of memory dies of a memory module using an exclusive-or (XOR) encoding process. Second encoded data is generated by performing a second encoding of the data included within each of the plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on the data included within each of the plurality of memory dies of the memory module using the first encoded data, the second encoded data, an XOR decoding process, and a cyclic code error correction process.

System and method for protecting data using cyclic properties of error correcting code

A method, computer program product, and computing system for defining one or more groups for data included within one or more groups of memory dies included within a memory module, thus defining a first group of parity bit groups; defining a parity bit for each memory die included within the one or more groups of memory dies, thus defining a plurality of parity bits; and defining one or more parity bit groups for the plurality of parity bits, thus defining a second group of parity bit groups.

Low complexity system and method for detection and correction of data with additional metadata from corruption

A method, computer program product, and computing system for defining one or more encoded symbols for data included within each of a plurality of memory dies of a memory module to define one or more groups of encoded symbols; generating Reed-Solomon parities for each group of encoded symbols; and recovering one or more portions of the data included within each of the plurality of memory dies of the memory module in the event of data corruption or die failure using one or more of the encoded symbols and the Reed-Solomon parities.

System and method for protecting data

The disclosure herein describes training and using an uncorrectable error (UE) state prediction model based on telemetry error data. Sets of UE state labels and non-UE state labels are generated from a first set of collected telemetry data, wherein the UE state labels each reference a UE and telemetry data of an interval prior to the referenced UE. Statistical features are extracted from telemetry data of the sets of UE state labels and non-UE state labels, and the extracted statistical features are used to train a UE state prediction model. A second set of collected telemetry data is obtained, and a UE event is predicted based on the second set of collected telemetry data using the trained UE state prediction model. A preventative operation is performed on a memory page of the system based on the predicted UE event, whereby the predicted UE event is prevented from occurring.

Training and using a memory failure prediction model

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

Semiconductor device with modified access and associated methods and systems

A memory controller may receive memory data to be stored on a memory. A memory controller may receive metadata related to the memory data. The metadata may be selected from a predetermined list of metadata. A memory controller may identify an encoding polynomial of a plurality of polynomials that is associated with the metadata, each polynomial of the plurality of polynomials associated with different metadata from the predetermined list of metadata. A memory controller may generate a codeword using the encoding polynomial of the plurality of polynomials and the memory data.

Devices, systems, and methods for encoding and decoding codewords

Methods, apparatuses, and systems related to securing memory data are described. A hardware circuit is configured to encrypt and decrypt memory data using a scrambling key unique to a computing process processing the memory data. In writing the memory data, the hardware circuit generates scrambled memory data based on encrypting the memory data according to the security key. The scrambled memory data is stored for the write operation instead of the memory data. When the same process reads back the scrambled data, the same security key can be used to decrypt the scrambled data and recover the initial unscrambled memory data.

Data security for memory and computing systems

A memory controller maintains a mapping of target ranges in system memory space interleaved two-ways across locations in a three-rank environment. For each range of the target ranges, the mapping comprises a two-way interleaving of the range across two ranks of the three-rank environment and offsets from base locations in the two ranks. At least one of the ranges has offsets that differ relative to each other. Such offsets allow the three ranks to be fully interleaved, two ways. An instruction to read data at a rank-agnostic location in the diverse-offset range causes the memory controller to map the rank-agnostic location to two interleaved locations offset different amounts from their respective base locations in their ranks. The controller may then affect the transfer of the data at the two interleaved locations.

Two-way interleaving in a three-rank environment

Embodiments of the disclosure are drawn to apparatuses, systems, methods for an internet of things (IoT) system to include edge devices that perform at least some functions without communicating with a cloud computing system. An edge device may include a memory with on-memory pattern matching capabilities. The edge device may perform pattern matching operations on data collected by the edge device or sensors in communication with the edge device. Based on results of the pattern matching operations, the edge device may perform various functions, such as transmitting data to the cloud computing system, activating an alarm, and/or changing a frequency at which data is transmitted.

Apparatuses and methods for inference processing on edge devices

Methods, apparatuses, and systems related to a data storage are described. Data targeted for storage is communicated to a memory device along with a scramble key. The scramble key is used to encode the target data, and the encoded data is stored at the memory device. For read operations, the encoded data is provided instead of the target data, and the target data is recovered outside of the memory device according to the scramble key.

Growing community of inventors

Boise, ID, United States of America

Brett Kenneth Dodds