Texas Instruments Corporation

Brett Earl Forejt

David John Baldwin

Mayank Garg

Jeff Berwick

John M Muza

Brandon J Beckham

David Hernandez-Garduno

A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off interval, a timer is started when the back-emf reaches a predetermined threshold, and after a predetermined delay has lapsed following the back-emf reaching the predetermined threshold during the first off interval, the LRA is driven over a drive interval having a length and drive strength. A second off interval is entered following the drive interval, and during the second off interval, the back-emf of the LRA is measured. During the second off interval, the timer is stopped when the back-emf reaches the predetermined threshold. The value from the timer that corresponds to the duration between the back-emf reaching the predetermined threshold during the first off interval and the back-emf reaching the predetermined threshold during the second off interval determines the length.

Method and apparatus to drive a linear resonant actuator at its resonant frequency

The present disclosure provides a reference one time programmable (OTP) cell, wherein the reference OTP cell can generate a reference bias current in at least a programmed-on configuration; a current mirror coupled to an output of the OTP cell, wherein the current mirror includes at least two gate-coupled field effect transistors (FETs); wherein a current gain of a second of the two FETS is a fraction less than one of a first of the at least two gate-coupled FETs; a programmable OTP memory bit element (OTPMBE) coupled to an input of the current mirror; and a comparator having an input coupled to a node between the OTPMBE and the current mirror.

Reference and read OTP sensors

A high-voltage driver amplifier for piezo haptics comprises an input amplifier having a gain greater than one, a first amplifier of an amplifier pair coupled to an output of the input amplifier, a second amplifier of the amplifier pair coupled to the output of the input amplifier, a first impedance coupled between an output of the first amplifier of the amplifier pair and an input of the input amplifier, and a second impedance coupled between the output of the first amplifier of the amplifier pair coupled to an output of the second amplifier of the amplifier pair. A substantially capacitive load is coupled to the output of the second amplifier. The substantially capacitive load is a piezo-capacitance, wherein the piezo-capacitance is employed in haptics. The second impedance, a shunt impedance, allows for a feedback of output variations between the first amplifier and the second amplifier over the first impedance.

High voltage driver amplifier for piezo haptics

An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Variable gain amplifier

Traditionally, switching amplifiers (i.e., class-D and class-G) with negative supply rails had issues with direct current (DC) power loss, included large external capacitors, had a comparative reduction in efficiency, and oftentimes included separate power management circuits. Here, a class-D amplifier is provided with an output stage that provides negative supply voltages, positive supply voltages, and ground. Essentially, this amplifier provides some of the benefits of the conventional amplifiers without the drawbacks.

Single supply class-D amplifier

A differential amplifier (-) includes an input stage () including first (M) and second (M) input transistors and first (A) and second (B) load devices. Sources of the first and second input transistors are connected together. Drains of the first and second input transistors are coupled by first () and second () conductors to the first and second load devices, respectively. Common mode feedback circuitry (A) including first (M), second (M), and third (M) transistors is combined with offset correction circuitry () including the second transistor and the third transistor. Sources of the first, second, and third transistors are coupled to a tail current source (). Drains of the second and third transistors are coupled to the first and second conductors, respectively. A common mode voltage (V) is applied to a gate of the first transistor. Offset trim voltages are applied to gates of the second and third transistors.

Combination trim and CMFB circuit and method for differential amplifiers

One embodiment of the invention includes a differential amplifier circuit. A first input stage generates first and second control voltages in response to a differential input signal. A second input stage generates third and fourth control voltages in response to the differential input signal. The first and second control voltages can be inversely proportional and the third and fourth control voltages can be inversely proportional. The circuit also includes a first output stage that is configured to set a magnitude of a first output voltage of a differential output signal at a first output node in response to the first and second control voltages. The circuit further includes a second output stage that is configured to set a magnitude of a second output voltage of the differential output signal at a second output node in response to the third and fourth control voltages.

Differential amplifier system

A new analog-to-digital (ADC) circuit and architecture and the corresponding method of implementation are provided. The analog input signal is converted into a modulated pulse stream such as by a pulse-width-modulation scheme. The time-duration width of the pulses are measured by a TDC (time-to-digital converter) and converted to a digital binary representation that is directly correlated with the voltage amplitude of the analog input signal. The circuit implementation is substantially free of switches and circuit issues such as associated with sigma-delta and switched-capacitor techniques for ADC's.

Class D analog-to-digital converter

A sigma delta class D device that uses a low pass filter to smooth the output waveform and eliminate high frequency switching noise from the feedback value includes: a first summing node having a positive input coupled to a signal input node; a second summing node having a first positive input coupled to an output of the first summing node and having an output coupled to a signal output node; a low pass filter having an input coupled to the output of the second summing node; an analog to digital converter having an input coupled to an output of the low pass filter; a third summing node having a positive input node coupled to an output of the analog to digital converter and a negative input node coupled to the output of the first summing node; and a feedback device coupled between an output of the third summing node and a negative input of the first summing node.

Sigma delta class D architecture which corrects for power supply, load and H-bridge errors

A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

Capacitor compensation in miller compensated circuits

A circuit and method is provided that provides an amplification stage to a comparator device that matches transistor transconductances to provide adequate amplification and employs diode coupled transistors to control the common mode output bias voltage. The circuit and method provides for a high gain comparator stage with control over output common mode voltage, while providing rail to rail output swing during differential mode without an external feedback to the comparator device.

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Garland, TX, United States of America

Brett Earl Forejt