Honeywell International Inc.

Brett Douglas Oliver

Christopher Brickner

Joseph Caltagirone

John D Profumo

David Jay Kessler

Barry Lawrence Allred

Alvin Badillo

Julie Pollock

A system for interfacing Ethernet with SpaceWire comprises a processor including an Ethernet MAC, and a bridge device connected between the processor and a SpaceWire subsystem or network. The bridge device comprises a SpaceWire physical interface that receives SpaceWire data packets, and an Ethernet MAC packet builder that includes digital logic for segmentation of the data packets into Ethernet compatible packet segments. An Ethernet media independent interface receives the packet segments from the packet builder and outputs the packet segments to the Ethernet MAC. The Ethernet media independent interface also receives Ethernet data packets transmitted from the Ethernet MAC. An Ethernet MAC packet extractor receives the Ethernet data packets from the Ethernet media independent interface and includes digital logic for performing reassembly of the Ethernet data packets into SpaceWire compatible data packets, which are sent to the SpaceWire physical interface for transmission to the SpaceWire subsystem or network.

Ethernet to spacewire bridge

A method for clock monitoring in a network is provided. The method comprises receiving a first network clock signal at a network device and comparing the first network clock signal to a local clock signal from a primary oscillator coupled to the network device.

Real time distributed embedded oscillator operating frequency monitoring

An apparatus comprises first and second modules configured to operate in a lockstep mode and a reset mode. Each of the first and second modules is configured to asynchronously enter the reset mode when a parent reset signal is asserted at the respective each module. Each of the first and second modules is configured to, in response to the asserted parent reset signal being negated at the respective each module, indicate to the respective other module that the respective each module is ready to exit the reset mode and exit the reset mode when the respective other module has also indicated that the respective other module is ready to exit the reset mode.

Clock and reset synchronization of high-integrity lockstep self-checking pairs

An apparatus and method of operating a cascadable, instant-fall-through First In, First Out (FIFO) buffer is provided. The method comprises receiving a first data element at an input of a FIFO buffer which includes a plurality of buffer slices including an output buffer slice wherein each of the plurality of buffer slices comprise a data register and a control bit register. A buffer slice is identified which is indicated for storing a data element based on a control bit register for the buffer slice and a control bit register of an adjacent buffer slice on an output side. When data is read from an output buffer slice the FIFO buffer, all data in other buffer slices are shifted down one slice closer to the output side of the FIFO buffer.

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Tampa, FL, United States of America

Brett Douglas Oliver