Nvidia Corporation

Transmeta Corporation

Other

Seiko Epson Corporation

Waymo LLC

Brett Coon

John Erik Lindholm

John R Nickolls

Ming Yiu Siu

Stuart F Oberman

Peter C Mills

Le Trong Nguyen

Johannes Wang

Yoshiyuki Miyayama

Godfrey P D'Souza

Paul S Serris

John P Banning

Lars Nyland

Simon S Moy

Brian Matthew Fahs

Gary M Tarolli

Matthew P Gerlach

Steven James Heinrich

Michael C Shebanow

Roger L Allen

Eric Hao

Malcolm J Wing

Linus Torvalds

Svetoslav D Tzvetkov

Weizhong Xu

Brian Choy

Patrick Gainer

John Stephen Montrym

Jack H Choquette

Emmett Michael Kilgariff

Brian Keith Cabral

John Matthew Burgess

Sean Jeffrey Treichler

David B Kirk

David Pardo Keppel

Alexander Lev Minkin

Norbert Juffa

John M Danskin

Timothy Campbell

Bryon S Nordquist

Samuel Kan Liu

Robert Steven Glanville

Rajeshwaran Selvanesan

Robert J Stoll

Nicholas Wang

Stewart Glenn Carlton

Anjana Rajendran

Ian Buck

Robert C Keller

Charles McCarver

Filip Perich

Kevin Duncklee

Henry Packard Moreton

Guillermo Juan Rozas

Stephen Donald Lew

Cheryl D Senter

Jered Wierzbicki

Charles R Price

Aravind Kalaiah

Daniel Salinas

Tommy Thorn

A method and a radar system are provided in the present disclosure. The radar system includes a radar unit having an antenna array configured to transmit and receive radar signal and a memory configured to store radar calibration parameters and radar channel parameters corresponding to the radar unit. The method provides for operation of the radar system. The radar system also includes a radar processor. The radar processor is configured to cause transmission of radar signals by the antenna array based on the radar channel parameters. The radar processor is also configured to process received radar signals based on the radar calibration parameters. The radar system further includes a central vehicle controller configured to operate a vehicle based on the processed radar signals.

Dynamic loading of radar unit configuration data based on changing radar parameters

Examples relate to near-field radar filters that can enhance measurements near a radar unit. An example may involve receiving a first set of radar reflection signals at a radar unit coupled to a vehicle and determining a filter configured to offset near-field effects of radar reflection signals received at the radar unit. In some instances, the filter depends on an azimuth angle and a distance for surfaces in the environment causing the first set of radar reflection signals. The example may also involve receiving, at the radar unit, a second set of radar reflection signals and determining, using the filter, an azimuth angle and a distance for surfaces in the environment causing the second set of radar reflection signals. The vehicle may be controlled based in part on the azimuth angle and the distance for the surfaces causing the second plurality of radar reflection signals.

Signal processing for near-field radar

A technique for managing a parallel cache hierarchy that includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

Instructions for managing a parallel cache hierarchy

A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Programmable graphics processor for multithreaded execution of programs

A method for managing a parallel cache hierarchy in a processing unit. The method including receiving an instruction that includes a cache operations modifier that identifies a level of the parallel cache hierarchy in which to cache data associated with the instruction; and implementing a cache replacement policy based on the cache operations modifier.

Cache operations and policies for a multi-threaded client

One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread.

Cooperative thread array reduction and scan operations

An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.

Indirect function call instructions in a synchronous parallel thread processor

A method for managing a parallel cache hierarchy in a processing unit. The method includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

One embodiment of the present invention sets forth a technique for coalescing memory barrier operations across multiple parallel threads. Memory barrier requests from a given parallel thread processing unit are coalesced to reduce the impact to the rest of the system. Additionally, memory barrier requests may specify a level of a set of threads with respect to which the memory transactions are committed. For example, a first type of memory barrier instruction may commit the memory transactions to a level of a set of cooperating threads that share an L1 (level one) cache. A second type of memory barrier instruction may commit the memory transactions to a level of a set of threads sharing a global memory. Finally, a third type of memory barrier instruction may commit the memory transactions to a system level of all threads sharing all system memories. The latency required to execute the memory barrier instruction varies based on the type of memory barrier instruction.

Coalescing memory barrier operations across multiple parallel threads

One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system performance. A credit-based technique may be used to control instruction by instruction scheduling for each warp in a group so that the group of warps is processed uniformly. A credit is computed for each warp and the credit contributes to a weight for each warp. The weight is used to select instructions for the warps that are issued for execution.

Credit-based streaming multiprocessor warp scheduling

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San Jose, CA, United States of America

Brett Coon