Advanced Micro Devices Corporation

Globalfoundries Inc.

National Semiconductor Corporation

Brett A Tischler

Kenneth James Kotlowski

Steven Kommrusch

Willard S Briggs

David T Harper

Carl D Dietz

Daniel Daugherty

Redentor Valencia

Rajeev Jayavant

Kevin A Scholander

David F Bremner

Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein the cache storage module is to initiate a storage of at least a portion of the compressed display data in the cache in response to an indication that the processing core is in an inactive mode. One method comprises, in response to an indication that a processor is in an inactive mode, transferring compressed display data from a frame buffer in memory to a cache associated with the processor, obtaining a first compressed display data from the cache, and decompressing the first compressed display data to generate a first uncompressed display data.

System and method for cache-based compressed display data storage

A method includes determining a cache width of a cache of a processing device and determining a block size of image data processed by the processing device. The method further includes prefetching a data block of image data from a memory component to a plurality of cache lines of the cache based on the cache width and the block size. A processing system includes a memory component, a cache and an execution pipeline coupled to the memory component and the cache. The execution pipeline is to determine a cache width of the cache, determine a block size of image data stored at the memory component, and prefetch a data block of image data from a memory component to a plurality of cache lines of the cache based on the cache width and the block size.

Data block transfer to cache

Whether a temperature of a portion of a die of an integrated circuit device having a central processing device and one or more peripheral components has exceeded a first temperature threshold is determined. In response to determining that the temperature of the portion of the die has exceeded the first temperature threshold, a first thermal reduction process for a first peripheral component of the one or more peripheral components is selected and the first thermal reduction process for the first peripheral component is implemented.

Thermal throttling of peripheral components in a processing device

A method for delayed memory access request arbitration includes dispatching a first memory access request to a memory controller and dispatching a second memory access request to the memory controller in response to an anticipated completion of a memory access operation represented by the first memory access request. Another method includes receiving a first memory access request at a bus interface unit at a first time, dispatching a second memory access request to a memory controller at a second time subsequent to the first time, receiving a third memory access request at the bus interface unit at a third time subsequent to the second time, dispatching the third memory access request to the memory controller at a fourth time subsequent to the third time and dispatching the first memory access request to the memory controller at a fifth time subsequent to the fourth time.

Delayed memory access request arbitration

A method includes logically organizing rasterized image data into a first matrix of pixel tiles and individually rotating each pixel tile so as to generate a corresponding pixel tile of a second matrix representing an orthogonal representation of the first matrix. Each pixel tile represents a set of buffer lines of a frame buffer storing rasterized image data. The pixel tile is rotated by accessing and storing each buffer line of pixel data in a set of tile buffers such that the pixel data for each pixel in the same column position of an adjacent row is stored in a different tile buffer so that the set of tile buffers can be individually accessed to obtain pixel data for a set of pixels in the same column position in adjacent rows. This obtained pixel data is written to a second frame buffer as a row of pixel data for the corresponding pixel tile of the second matrix.

System and method for rotating rasterized image data

A first scan data is received at a first scan chain and a representation of the first scan data is subsequently provided from the first scan chain to a second scan chain to test the second scan chain in response to a first value at a first bond pad. The first scan chain is bypassed to receive the first scan data at the second scan chain in response to a second value at the first bond pad.

Method of configuring a system and system therefor

A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.

Memory access request arbitration

A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank identifier based on a value at the first bit location of the linear address. Another method includes receiving, at a memory controller coupled to a multiple-bank memory, input indicating a mapping of values at identified bit locations of a linear address to corresponding values of a memory address output. The memory address output includes a bank identifier based on a value at one or more of at least three bit locations of the linear address and a value of the input is programmable.

Programmable interleaving in multiple-bank memories

There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.

System and method for machine specific register addressing in external devices

A processing system comprising: i) a processor core; ii) a memory; iii) a plurality of peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the peripheral devices for transferring bus transactions between the processor core, the memory, and the peripheral devices. The communication bus comprises a bus controller for receiving memory access request data associated with a first memory access to a first location in the memory by a first one of the peripheral devices and transferring the received memory access request data to at least one memory address pin used to access the memory.

Apparatus and method for viewing data processor bus transactions on address pins during memory idle cycles

A processing system comprising: i) processor core; ii) a memory; iii) N peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the N peripheral devices that transfers bus request packets between the processor core, the memory, and the N peripheral devices. The communication bus comprises debug circuitry for capturing bus transaction data associated with a bus transaction between a first of the peripheral devices and a second of the peripheral devices and transferring the captured bus transaction data to an external test device.

Bus architecture using debug packets to monitor transactions on an internal data processor bus

A master unit and a slave unit in a data processor are coupled together by a data bus. The master unit sends data transactions to the slave unit through the data bus and the slave unit executes the data transactions. The present invention comprises an apparatus and method for executing a data transaction either (1) by executing the data transaction 'in order' with respect to other data transactions received by the slave unit, or (2) by executing the data transaction 'out of order' with respect to other data transactions received by the slave unit. The master unit assigns a priority identifier to each data transaction. The slave unit reads the priority identifier to determine whether to execute the data transaction &#x201c;in order&#x201d; or &#x201c;out of order&#x201d; with respect to the other data transactions.

Apparatus and method for sending in order data and out of order data on a data bus

For use with a memory controller in a data processor that is capable of executing memory refresh requests to refresh a memory of the data processor, an apparatus and method is disclosed for scheduling execution of the memory refresh requests. The apparatus comprises a periodic memory refresh hint unit that is capable of sending to the memory controller a data signal that comprises a periodic memory refresh hint. The periodic memory refresh hint informs the memory controller of an optimal time for a memory refresh to occur. The memory controller may immediately execute a memory refresh request when it arrives or delay the execution of the memory refresh request until a more opportune time. This feature enables the memory controller to reduce memory access latency in scheduling memory transactions.

Apparatus and method for isochronous arbitration to schedule memory refresh requests

A system clock circuit that provides a high-speed reference clock signal for operating an integrated circuit. The system clock circuit comprises a frequency combiner circuit that receives a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1. The second external clock signal is phase-shifted by P degrees with respect to the first external clock signal. The frequency combiner circuit generates from the first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2. The system clock circuit also comprises a clock selection circuit that selectively applies the first output clock signal to the integrated circuit.

Precision bypass clock for high speed testing of a data processor

A dynamically configurable portion of a cache shared between central processing and graphics units in a highly integrated multimedia processor is engaged as a secondary level in a hierarchical texture cache architecture. The graphics unit includes a small multi-ported Ltexture cache local to its 2D/3D pipeline that is backed by the relatively large, single ported portion of the shared cache. Leveraging the shared cache as a secondary level texture cache reduces system memory bandwidth and die size without significant sacrifice in performance.

Growing community of inventors

Longmont, CO, United States of America

Brett A Tischler