Texas Instruments Corporation

Apple Inc.

R2 Semiconductor, Inc.

Other

Bret Rothenberg

James E C Brown

Vehbi Calayir

Lawrence M Burns

James E Brown

Chengrui Le

Venkataraman V Iyer

ChienKuo Tien

Rodrigo Calderon Rico

James EC Brown

A method and light-emitting diode (LED) device configured to compensate for crosstalk between rows of the LED device.

Row crosstalk mitigation

Aspects of the subject technology relate to an electronic device with a display. The display includes a first array of light-emitting diodes of a backlight unit to generate backlight for the display with each LED including an anode and a cathode. A first switch selectively couples a power supply voltage to a common anode of the first array of LEDs to control illumination of the first array of LEDs. A first discharge switch selectively couples a first voltage level to the common anode of the first array of LEDs to discharge the common anode to prevent an undesired current path through the first array of LEDs and associated undesired illumination.

Display backlighting systems with cancellation architecture for canceling ghosting phenomena

Aspects of the subject technology relate to an electronic device with a display. The display includes an array of light-emitting diodes. The array includes a plurality of subarrays of the light-emitting diodes. At least one driver circuit is coupled to the array of light-emitting diodes. The at least one driver circuit is configured to generate an adaptive pulse-width modulated (PWM) signal to control at least one subarray of the plurality of subarrays of the light-emitting diodes. The adaptive PWM signal is designed with each pulse of a group having a pulse width W, each pulse width being reduced until reaching a threshold pulse width, and one pulse being removed from the group of pulses.

Display backlighting systems and methods for adaptive pulse width modulation and modulo pulse width modulation

A lighting system includes light fixtures not in communications with and not synchronized with one another, and one or more light sensors. Each light fixture separately emits data encoded visible light including light fixture information encoded therein in a manner that avoids visually perceptible flicker and enables light fixture information emitted by one light fixture to be distinguished from light fixture information emitted by other light fixtures. The light fixture information is encoded into data encoded visible light such that a difference between different levels of the data encoded visible light is indicative of an illumination capability of the light fixture and such that visually perceptible flicker is avoided. Each light sensor separately receives portions of data encoded light visible light emitted by multiple light fixtures and separately determines the identity of and the maximum and present illumination contributions for each light fixture.

Methods and systems for encoding and decoding visible light with data and illumination capability

Embodiments for at least one method and apparatus for controlling timing of switch control signals of a switching voltage regulator disclosed. One method includes generating a regulated output voltage based upon a switching voltage, generating the switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and controlling, by a delay block, the closing and opening of the series switch element and a shunt switch element. The delay block control includes receiving, by the delay block, a timing signal, generating a one of a series switch control signal and a shunt switch control signal by controllably delaying the timing signal with a first delay, and generating one other of the series switch control signal and the shunt switch control signal by inverting, and controllably delaying the timing signal with a second delay.

Delay block for controlling a dead time of a switching voltage regulator

Embodiments for at least one method and apparatus of controlling a bypass resistance of a voltage regulator are disclosed. One method includes generating a regulated output voltage based upon a switching voltage. The switching voltage is generated through controlled closing and opening of a series switch element and a shunt switch element, the series switch element and the shunt switch element being connected between voltages based on an input voltage. Control of a duty cycle of the switching voltage is provided by sensing and feeding back the regulated output voltage. The bypass resistance is controlled based on an integration of a difference between the duty cycle and a maximum duty cycle.

Voltage regulator bypass resistance control

Embodiments for at least one method and apparatus of controlling a bypass resistance of a voltage regulator are disclosed. One method includes generating a regulated output voltage based upon a switching voltage. The switching voltage is generated through controlled closing and opening of a series switch element and a shunt switch element, the series switch element and the shunt switch element being connected between voltages based on an input voltage. A control of a duty cycle of the switching voltage is provided by sensing and feeding back the regulated output voltage. The bypass resistance is controlled based on a parameter related to the duty cycle, wherein the control of the duty cycle is persistent during the control of the bypass resistance.

A full-duplex transceiver using a method immunizing itself against self-jamming. The transceiver includes a receiver and a transmitter. The receiver includes a frequency immunization converter and a high pass IF filter. The transmitter transmits a TX signal. The receiver receives an RX signal and simultaneously receives a portion of the power of the TX signal as an undesired TX jamming signal. The frequency immunization converter uses the center frequency of the TX signal for downconverting the RX signal to an IF signal and simultaneously downconverting the TX jamming signal to near zero frequency. The high pass IF filter passes the IF signal and blocks the signal at near zero frequency. As a consequence of the downconversion using the TX frequency, a second LO frequency is controlled for avoiding image frequencies.

Full duplex transceiver having a method for immunizing itself against self-jamming

A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.

Gaussian minimum shift key transmitter with feedforward phase compensation

Method and apparatus for measuring phase error of a modulated signal

An apparatus and a method having a low sampling clock frequency for converting a digital signal having IF frequency channels to an analog IF signal. A DAC uses the sampling signal for converting the digital signal to the analog IF signal. A high-low RFLO signal generator generates an RFLO signal that is controlled to switch between a first RFLO frequency below a desired RF frequency band and a second RFLO frequency above the desired RF frequency band. The RF upconverter uses the first RFLO frequency for upconverting IF frequency channels into RF frequency channels in the lower half of the RF frequency band and uses the second RFLO frequency for upconverting the same IF frequency channels into different RF frequency channels in the upper half of the RF frequency band, thereby enabling the DAC to use a lower frequency sampling signal.

Transmitter and method having a low sampling frequency for digital to analog conversion

A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator and an IQ balancer. The IQ coefficient calculator computes a set of correction coefficients for each packet from the I and Q signals in an IQ measurement section at the front of the packet. The IQ balancer uses the correction coefficients for correcting the I/Q gain and I/Q phase errors on a packet-by-packet basis. Optionally, delay devices delay the I and Q signals so that the correction coefficients may be applied to the entire packet, or the portion of the packet in the IQ measurement section is passed through uncorrected and the correction coefficients are applied to the packet after the IQ measurement section.

Growing community of inventors

Los Altos, CA, United States of America

Bret Rothenberg