Ampere Computing LLC

Bret Leslie Toll

Benjamin C Chaffin

Jonathan Christopher Perry

George Van Horn Leming, Iii

John Gregory Favor

Stephan Jourdan

Nagi Aboulenein

Michael Stephen Chin

Jacob Daniel Morgan

David Nuechterlein

Michael Spradling

Benjamin Crawford Chaffin

A compute node capable of enhanced performance and/or energy savings is proposed. The proposed compute node may check whether a last instruction of a first group—retrieved in a first decode cycle—is potentially a fusible instruction. If so, the proposed compute node may refrain from decoding the last instruction in the first decode cycle. Instead, the proposed compute node may determine if a first instruction of a second group of instructions retrieved in a second decode cycle (subsequent to the first decode cycle) is fusible with the last instruction of the first group. If so, the two instructions may be fused to a single micro-operation.

Mechanism for instruction fusion

Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides multiple processors including a remote processor. The remote processor receives, from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation, and subsequently receives an IFPS request from the issuing processor. The remote processor determines that any previously received TLBI requests including the most recent TLBI request have completed. Upon receiving the IFPS request, the remote processor determines that all instructions within a fetch pipeline portion that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion of an instruction processing circuit to an execution pipeline portion of the instruction processing circuit. The remote processor then performs a data synchronization barrier (DSB) operation, and issues a synchronization acknowledgement to the issuing processor.

Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices

Mitigation of return stack buffer side channel attacks in a processor. Detecting a side channel attack or a fault in a return from a function call in the processor includes receiving a return exception level indication (or e.g., a return security level indication) indicating the exception level associated with the return and comparing the exception level associated with the return to the exception level (or security level) associated with the return address. The return exception level indicator may be received in conjunction with a return indication. The processing circuit accesses the first entry of the return stack buffer, which indicates the return address of the function call, and also accesses an exception level associated with the return address. The processing circuit compares the exception level associated with the return address to the exception level associated with the return to determine whether to use the return address in a prediction of instruction flow.

Mitigation of return stack buffer side channel attacks in a processor

A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.

Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer

A data processing system includes a store datapath configured to perform tag checking in a store operation to a store address associated with a cache line in a memory. The store datapath includes a cache lookup circuit configured to pre-load a store cache line that is to be updated in the store operation, wherein the store cache line comprises the cache line in the memory to be updated in the store operation. The store datapath also includes a tag check circuit configured to compare a store address tag associated with the store address to a store operation tag associated with the store operation. The data processing system may include a load datapath configured to perform tag checking in a load operation from a load cache line in the memory by comparing a load address tag associated with the load address to a load operation tag associated with the load operation.

Growing community of inventors

Santa Clara, CA, United States of America

Bret Leslie Toll