Micron Technology Incorporated

Bret Addison Johnson

Hari Giduturi

Vijayakrishna J Vankayala

Jung-Hwa Choi

A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

Tuned datapath in stacked memory device

Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include an interfacing die and at least one additional die communicatively coupled to each other through an internal bus. The interfacing die may be configured to provide a combined external interface for the coupled dies. For the die-to-die communications, a target die may coordinate transfer of communicated data to the internal interface according to a timing signal generated by a source external to the at least one additional die.

Apparatus with access control mechanism and methods for operating the same

The systems and methods described herein consider a first channel width of transistors of driver circuitry, where the first channel width may be set to match a second channel width of a power control transistor. A control circuit, for example, may match a second channel width of a set of power control transistors to the first channel width by turning on one or more of the set of power control transistors. Matching the width of the switches of driver circuitry and the width of the set of power control transistors may reduce losses by helping to maintain impedances of the driver circuitry.

Output driver with strength matched power gating

Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include a master die and a set of slave dies communicatively coupled to each other through an internal bus. The master die may be configured to provide a combined external interface for both the master die and the set of slave dies. For the die-to-die communications, a target die may coordinate transfer of communicated data to the internal interface according to a timing signal generated by a source external to the set of slave dies.

As described, a device may include detection circuitry to detect a deck of a memory array. The deck may include a conductive identifier coupled between a logic high voltage node and the detection circuitry a control circuit coupled to the detection circuit. The control circuit may perform operations including transmitting a test enable signal to the detection circuitry. The detection circuitry may generate a valid signal indicative of an existence of the conductive identifier of the deck in response to the test enable signal. The operations may also include the control circuit receiving the valid signal from the detection circuitry and adjusting a memory operation associated with the memory array based at least in part on the valid signal.

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Folsom, CA, United States of America

Bret Addison Johnson